Datasheet
2017 Microchip Technology Inc. DS00002348A-page 49
KSZ8873MLL/FLL/RLL
The following registers are used to enable features that are assigned on a per port basis. The register bit assignments
are the same for all ports, but the address for each port is different, as indicated.
TABLE 4-7: PORT REGISTERS (REGISTERS 16 - 95)
Bit Name R/W Description Default
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
7
Broadcast Storm
Protection Enable
R/W
1 = enable broadcast storm protection for ingress
packets on port
0 = disable broadcast storm protection
0
6
DiffServ Priority
Classification Enable
R/W
1 = enable DiffServ priority classification for ingress
packets (IPv4) on port
0 = disable DiffServ function
0
5
802.1p Priority Clas-
sification Enable
R/W
1 = enable 802.1p priority classification for ingress
packets on port
0 = disable 802.1p
0
4-3
Port-based Priority
Classification
R/W
00 = ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
01 = ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
10 = ingress packets on port will be
classified as priority 2 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
11 = ingress packets on port will be
classified as priority 3 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
Note: “DiffServ,” “802.1p,” and port priority can be
enabled at the same time. The OR’ed result of 802.1p
and DSCP overwrites the port priority.
00
2 Tag Insertion R/W
1 = when packets are output on the port, the switch
will add 802.1p/q tags to packets without 802.1p/q
tags when received. The switch will not add tags to
packets already tagged. The tag inserted is the
ingress port’s “port VID”.
0 = disable tag insertion
Note: For the tag insertion available, the register 194
bits [5:0] have to be set first.
0
1 Tag Removal R/W
1 = when packets are output on the port, the switch
will remove 802.1p/q tags from packets with 802.1p/q
tags when received. The switch will not modify pack-
ets received without tags.
0 = disable tag removal
0
0 TXQ Split Enable R/W
1 = split TXQ to 4 queue configuration. It cannot be
enable at the same time with split 2 queue at register
18, 34, 50 bit 7.
0 = no split, treated as 1 queue configuration
0
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
7 Sniffer Port R/W
1 = Port is designated as sniffer port and will transmit
packets that are monitored.
0 = Port is a normal port
0