Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 45
KSZ8873MLL/FLL/RLL
0 Reserved R/W
Reserved
Do not change the default value.
0
Register 5 (0x05): Global Control 3
7
802.1Q VLAN
Enable
R/W
1 = 802.1Q VLAN mode is turned on. VLAN table
needs to set up before the operation.
0 = 802.1Q VLAN is disabled.
0
6
IGMP Snoop Enable
on Switch MII
Interface
R/w
1 = IGMP snoop is enabled. All IGMP packets will be
forwarded to the Switch MII port.
0 = IGMP snoop is disabled.
0
5 Reserved RO
Reserved
Do not change the default values.
0
4 Reserved RO
Reserved
Do not change the default values.
0
3
Weighted Fair
Queue Enable
R/W
0 = Priority method set by the registers 175-186 bit [7]
= 0 for port 1, port 2, and port 3.
1 = Weighted Fair Queuing enabled. When all four
queues have packets waiting to transmit, the band-
width allocation is q3:q2:q1:q0 = 8:4:2:1.
If any queues are empty, the highest non-empty
queue gets one more weighting. For example, if q2 is
empty, q3:q2:q1:q0 becomes (8+1):0:2:1.
0
2 Reserved RO
Reserved
Do not change the default values.
0
1 Reserved RO
Reserved
Do not change the default values.
0
0 Sniff Mode Select R/W
1 = will do RX AND TX sniff (both source port and
destination port need to match)
0 = will do RX OR TX sniff (either source port or desti-
nation port needs to match). This is the mode used to
implement RX only sniff.
0
Register 6 (0x06): Global Control 4
7 Reserved RO
Reserved
Do not change the default values.
0
6
Port 3 Duplex Mode
Selection
R/W
1 = Enable Port 3 MII to half-duplex mode.
0 = Enable Port 3 MII to full-duplex mode.
0
Pin P1LED0
strap option.
Pull-up(1): Half -
duplex mode
Pull-down(0):
Full-duplex
mode (default)
Note: P1LED0
has internal pull-
down.
TABLE 4-6: GLOBAL REGISTERS (0-15) (CONTINUED)
Bit Name R/W Description Default