Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 40  2017 Microchip Technology Inc.
11
10 Half
Capable
RO
1 = 10BASE-T half-duplex capable
0 = Not 10BASE-T half-duplex capable
1 Always 1
10-7 Reserved RO — 0000 —
6
Preamble
Suppressed
RO Not Supported 0 —
5 AN Complete RO
1 = Auto-negotiation complete
0 = Auto-negotiation not completed
0
Reg. 30, bit 6
Reg. 46, bit 6
4
Far-End
Fault
RO
1 = Far-end fault detected
0 = No far-end fault detected
0 Reg. 31, bit 0
3 AN Capable RO
1 = Auto-negotiation capable
0 = Not auto-negotiation capable
1
Reg. 28, bit 7
Reg. 44, bit 7
2 Link Status RO
1 = Link is up
0 = Link is down
0
Reg. 30, bit 5
Reg. 46, bit 5
1 Jabber Test RO Not Supported 0 —
0
Extended
Capable
RO 0 = Not extended register capable 0 —
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High
15-0 PHYID High RO High order PHYID bits 0x0022 —
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low
15-0 PHYID Low RO Low order PHYID bits 0x1430 —
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability
15 Next Page RO Not Supported 0 —
14 Reserved RO — 0 —
13 Remote Fault RO Not Supported 0 —
12-11 Reserved RO — 00 —
10 Pause R/W
1 = Advertise pause ability
0 = Do not advertise pause ability
1
Reg. 28, bit 4
Reg. 44, bit 4
9 Reserved R/W — 0 —
8 Adv 100 Full R/W
1 = Advertise 100 full-duplex ability
0 = Do not advertise 100 full-duplex ability
1
Reg. 28, bit 3
Reg. 44, bit 3
7 Adv 100 Half R/W
1 = Advertise 100 half-duplex ability
0 = Do not advertise 100 half-duplex ability
1
Reg. 28, bit 2
Reg. 44, bit 2
6 Adv 10 Full R/W
1 = Advertise 10 full-duplex ability
0 = Do not advertise 10 full-duplex ability
1
Reg. 28, bit 1
Reg. 44, bit 1
5 Adv 10 Half R/W
1 = Advertise 10 half-duplex ability
0 = Do not advertise 10 half-duplex ability
1
Reg. 28, bit 0
Reg. 44, bit 0
4-0
Selector
Field
RO 802.3 00001 —
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability
15 Next Page RO Not Supported 0 —
14 LP ACK RO Not Supported 0 —
13 Remote Fault RO Not Supported 0 —
12-11 Reserved RO — 00 —
TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED)
Bit Name R/W Description Default Reference