Datasheet
2017 Microchip Technology Inc. DS00002348A-page 39
KSZ8873MLL/FLL/RLL
4.2 Register Descriptions
TABLE 4-2: REGISTER DESCRIPTIONS
Bit Name R/W Description Default Reference
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control
15 Soft Reset RO Not Supported 0 —
14 Loopback R/W
1 = Perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
0 = Normal operation
0
Reg. 29, bit 0
Reg. 45, bit 0
13 Force 100 R/W
1 = 100 Mbps
0 = 10 Mbps
0
Reg. 28, bit 6
Reg. 44, bit 6
12 AN Enable R/W
1 = Auto-negotiation enabled
0 = Auto-negotiation disabled
1
Reg. 28, bit 7
Reg. 44, bit 7
11 Power Down R/W
1 = Power down
0 = Normal operation
0
Reg. 29, bit 3
Reg. 45, bit 3
10 Isolate RO Not Supported 0 —
9Restart ANR/W
1 = Restart auto-negotiation
0 = Normal operation
0
Reg. 29, bit 5
Reg. 45, bit 5
8
Force Full-
Duplex
R/W
1 = Full-duplex
0 = Half-duplex
0
Reg. 28, bit 5
Reg. 44, bit 5
7 Collision Test RO Not Supported 0 —
6 Reserved RO — 0 —
5 Hp_mdix R/W
1 = HP Auto MDI/MDI-X mode
0 = Microchip Auto MDI/MDI-X mode
1
Reg. 31, bit 7
Reg. 47, bit 7
4Force MDIR/W
1 = Force MDI (transmit on RXP/RXM pins)
0 = Normal operation (transmit on TXP/TXM
pins)
0
Reg. 29, bit 1
Reg. 45, bit 1
3
Disable
MDIX
R/W
1 = Disable auto MDI-X
0 = Enable auto MDI-X
0
Reg. 29, bit 2
Reg. 45, bit 2
2
Disable Far-
End Fault
R/W
1 = Disable far-end fault detection
0 = Normal operation
0 Reg. 29, bit 4
1
Disable
Transmit
R/W
1 = Disable transmit
0 = Normal operation
0
Reg. 29, bit 6
Reg. 45, bit 6
0 Disable LED R/W
1 = Disable LED
0 = Normal operation
0
Reg. 29, bit 7
Reg. 45, bit 7
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status
15 T4 Capable RO 0 = Not 100BASE-T4 capable 0 —
14
100 Full
Capable
RO
1 = 100BASE-TX full-duplex capable
0 = Not capable of 100BASE-TX full-duplex
1 Always 1
13
100 Half
Capable
RO
1 = 100BASE-TX half-duplex capable
0 = Not 100BASE-TX half-duplex capable
1 Always 1
12
10 Full
Capable
RO
1 = 10BASE-T full-duplex capable
0 = Not 10BASE-T full-duplex capable
1 Always 1