Datasheet

KSZ8873MLL/FLL/RLL

DS00002348A-page 30  2017 Microchip Technology Inc.

Learning state: only packets to and from the processor are forwarded. Learning is enabled.

Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.”

Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU

packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The

processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is

enabled on the port in this state.

Ports in Forwarding states fully participate in both data forwarding and MAC learning.

Forwarding state: packets are forwarded and received normally. Learning is enabled.

Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0.”

Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU

packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor. The

processor may send packets to the port(s) in this state, see “Tail Tagging Mode” section for details. Address learning is

enabled on the port in this state.

RSTP uses only one type of BPDU called RSTP BPDUs. They are similar to STP Configuration BPDUs with the excep-

tion of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.

3.7 Tail Tagging Mode

The Tail Tag is only seen and used by the port 3 interface, which should be connected to a processor. It is an effective

way to retrieve the ingress port information for spanning tree protocol IGMP snooping and other applications. The Bit 1

and bit 0 in the one byte tail tagging is used to indicate the source/destination port in port 3. Bit 3 and bit 2 are used for

the priority setting of the ingress frame in port 3. Other bits are not used. The Tail Tag feature is enable by setting register

3 bit 6.

FIGURE 3-7: TAIL TAG FRAME FORMAT

TABLE 3-13: TAIL TAG RULES

Ingress to Port 3 (Host to KSZ8873)

Bit [1,0] Destination Port

0,0 Normal (address lookup)

0,1 Port 1

1,0 Port 2

1,1 Port 1 and 2

Bit [3,2] Frame Priority

0,0 Priority 0

0,1 Priority 1

1,0 Priority 2

1,1 Priority 3

Egress from Port 3 (KSZ8873 to Host)

Bit [0] Source Port

0Port 1

1Port 2

Preamble DA TCI

866 2

length LLC Data Tail Tag

2 46-1500 1

FCS

Bytes 2

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