Datasheet

KSZ8873MLL/FLL/RLL
DS00002348A-page 26  2017 Microchip Technology Inc.
3.3.11 SERIAL MANAGEMENT INTERFACE (SMI)
The SMI is the KSZ8873MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8873MLL/FLL/RLL
configuration registers. This interface allows an external device to completely monitor and control the states of the
KSZ8873MLL/FLL/RLL.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8873MLL/FLL/RLL device.
• Access to all KSZ8873MLL/FLL/RLL configuration registers. Register access includes the Global, Port and
Advanced Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31].
Table 3-9 depicts the SMI frame format.
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8873MLL/FLL/RLL registers 0-196 (0x00 – 0xC6), the following applies:
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
• TA bits [1:0] are ‘Z0’ means the processor MDIO pin is changed to input Hi-Z from output mode and the followed
‘0’ is the read response from device.
• TA bits [1:0] are set to ‘10’ when write registers.
• Registers are 8 data bits wide.
- For read operation, data bits [15:8] are read back as 0’s.
- For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
3.4 Advanced Switch Functions
3.4.1 BYPASS MODE
The KSZ8873MLL/FLL/RLL also offers a bypass mode that enables system-level power saving. When the CPU (con-
nected to Port 3) enters a power saving mode of power down or sleeping mode, the CPU can control pin 27 SMTXER3/
MII_LINK_3, which can be tied high so that the KSZ8873MLL/FLL/RLL detects this change and automatically switches
to the bypass mode. In this mode, the switch function between Port 1 and Port 2 is sustained. The packets with DA to
Port 3 will be dropped and will bypass the internal buffer memory, making the buffer memory more efficient for the data
transfer between Port 1 and Port 2.
TABLE 3-8: MII MANAGEMENT FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits[15:0] Idle
Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
TABLE 3-9: SERIAL MANAGEMENT INTERFACE (SMI) FRAME FORMAT
Preamble
Start of
Frame
Read/
Write OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits[15:0] Idle
Read 32 1’s 01 00 1xRRR RRRRR Z0 0000_0000_DDDD_DDDD Z
Write 32 1’s 01 00 0xRRR RRRRR 10 xxxx_xxxx_DDDD_DDDD Z