Datasheet

 2017 Microchip Technology Inc. DS00002348A-page 25
KSZ8873MLL/FLL/RLL
The KSZ8873RLL filters error frames and, thus, does not implement the RX_ER output signal. To detect error frames
from RMII PHY devices, the SMTXER3 input signal of the KSZ8873RLL is connected to the RXER output signal of the
RMII PHY device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, tie MII signals SMTXD3[3:2] and SMTXER3 to ground if they are not used.
The KSZ8873RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8873RLL
devices to be connected back-to-back. Ta b le 3 - 7 shows the KSZ8873RLL RMII pin connections with an external RMII
PHY and an external RMII MAC, such as another KSZ8873RLL device.
3.3.10 MII MANAGEMENT (MIIM) INTERFACE
The KSZ8873MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8873MLL/FLL/RLL. An external device with MDC/MDIO capability is used to read the PHY status or configure the
PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification and refer
to 802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8873MLL/FLL/RLL device.
• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM regis-
ters [29, 31].
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
Table 3-8 depicts the MII Management Interface frame format.
TXD0 Input Output Transmit data bit 0 SMTXD30 (input)
RX_ER Output Input (not required) Receive error (not used)
————
SMTXER3 (input)
Connects to RX_ER
signal of RMII PHY
device
TABLE 3-7: RMII SIGNAL CONNECTIONS
KSZ8873RLL
PHY-MAC Connections
Pin Descriptions
KSZ8873RLL
MAC-MAC Connections
External PHY
Signals
KSZ8873RLL MAC
Signals
KSZ8873RLL MAC
Signals
External MAC
Signals
REF_CLK REFCLKI_3 Reference Clock REFCLKI_3 REF_CLK
TX_EN SMRXDV3
Carrier sense/
Receive data valid
SMRXDV3 CRS_DV
TXD1 SMRXD31 Receive data bit 1 SMRXD31 RXD1
TXD0 SMRXD30 Receive data bit 0 SMRXD30 RXD0
CRS_DV SMTXEN3 Transmit enable SMTXEN3 TX_EN
RXD1 SMTXD31 Transmit data bit 1 SMTXD31 TXD1
RXD0 SMTXD30 Transmit data bit 0 SMTXD30 TXD0
RX_ER SMTXER3 Receive error (not used) (not used)
TABLE 3-6: RMII SIGNAL DESCRIPTION (CONTINUED)
RMII Signal Name
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8873RLL RMII
Signal Direction