Datasheet
2017 Microchip Technology Inc. DS00002348A-page 23
KSZ8873MLL/FLL/RLL
3.3.7.8 Port Individual MAC Address and Source Port Filtering
The KSZ8873MLL/FLL/RLL provide individual MAC address for port 1 and port 2 respectively. They can be set at reg-
ister 142-147 and 148-153. With this feature, the CPU connected to the port 3 can receive the packets from two internet
subnets which has their own MAC address.
The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and
37 bit 6 is set to 1 respectively. For example, the packet will be dropped after it completes the loop of a ring network.
3.3.8 MII INTERFACE OPERATION
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u Standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by the KSZ8873MLL/FLL is connected to
the device’s third MAC. The interface contains two distinct groups of signals: one for transmission and the other for
reception. Tabl e 3 - 4 describes the signals used by the MII bus.
The MII operates in either PHY mode or MAC mode. The data interface is a nibble wide and runs at ¼ the network bit
rate (not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during
transmission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors.
For half-duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
The KSZ8873MLL/FLL does not provide the MRXER signal for PHY mode operation and the MTXER signal for MAC
mode operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indi-
cates a transmit error from the MAC device. Because the switch filters error frames, these MII error signals are not used
by the KSZ8873MLL/FLL. So, for PHY mode operation, if the device interfacing with the KSZ8873MLL/FLL has an
MRXER input pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with the KSZ8873MLL/
FLL has an MTXER input pin, it also needs to be tied low.
The KSZ8873MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link
status. If the host is power down, pin MII_LINK will go to high. In this case, no new ingress frames from port1 or port 2
will be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out.
3.3.9 RMII INTERFACE OPERATION
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Ports 10 Mbps and 100 Mbps data rates.
TABLE 3-4: MII SIGNALS
PHY Mode Connections
Pin Description
MAC Mode Connections
External MAC
Controller Signals
KSZ8873MLL/FLL
PHY Signals
External PHY
Signals
KSZ8873MLL/FLL
MAC Signals
MTXEN SMTXEN3 Transmit Enable MTXEN SMRXDV3
MTXER SMTXER3 Transmit Error MTXER (NOT USED)
MTXD3 SMTXD33 Transmit Data Bit 3 MTXD3 SMRXD33
MTXD2 SMTXD32 Transmit Data Bit 2 MTXD2 SMRXD32
MTXD1 SMTXD31 Transmit Data Bit 1 MTXD1 SMRXD31
MTXD0 SMTXD30 Transmit Data Bit 0 MTXD0 SMRXD30
MTXC SMTXC3 Transmit Clock MTXC SMRXC3
MCOL SCOL3 Collision Detection MCOL SCOL3
MCRS SCRS3 Carrier Sense MCRS SCRS3
MRXDV SMRXDV3 Receive Data Valid MRXDV SMTXEN3
MRXER (NOT USED) Receive Error MRXER SMTXER3
MRXD3 SMRXD33 Receive Data Bit 3 MRXD3 SMTXD33
MRXD2 SMRXD32 Receive Data Bit 2 MRXD2 SMTXD32
MRXD1 SMRXD31 Receive Data Bit 1 MRXD1 SMTXD31
MRXD0 SMRXD30 Receive Data Bit 0 MRXD0 SMTXD30
MRXC SMRXC3 Receive Clock MRXC SMTXC3