KSZ8873MLL/FLL/RLL Integrated 3-Port 10/100 Managed Switch with PHYs Features • Advanced Switch Features - IEEE 802.1q VLAN Support for Up to 16 Groups (Full Range of VLAN IDs) - VLAN ID Tag/Untag Options, Per Port Basis - IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis (Egress) - Programmable Rate Limiting at the Ingress and Egress on a Per Port Basis - Broadcast Storm Protection with Percent Control (Global and Per Port Basis) - IEEE 802.
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KSZ8873MLL/FLL/RLL Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ............................................................
KSZ8873MLL/FLL/RLL 1.0 INTRODUCTION 1.1 General Description The KSZ8873MLL/FLL/RLL are highly integrated 3-port switch-on-a-chip ICs in the industry’s smallest footprint. They are designed to enable a new generation of low port count, cost-sensitive, and power efficient 10/100 Mbps switch systems. Low power consumption, advanced power management, and sophisticated QoS features (e.g.
KSZ8873MLL/FLL/RLL 2.0 PIN DESCRIPTION AND CONFIGURATION 64-PIN 10 MM X 10 MM LQFP ASSIGNMENT, (TOP VIEW) VDDA_1.8 FXSD1 RSTN P2LED0 P2LED1 P1LED0 P1LED1 NC VDDCO GND VDDIO NC NC P3SPD P1FFC VDDC FIGURE 2-1: 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RXM1 RXP1 AGND TXM1 TXP1 VDDA_3.3 AGND ISET VDDA_1.
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS Pin Number Pin Name Type Note 2-1 1 RXM1 I/O Physical receive or transmit signal (– differential) 2 RXP1 I/O Physical receive or transmit signal (+ differential) 3 AGND GND 4 TXM1 I/O Physical transmit or receive signal (– differential) 5 TXP1 I/O Physical transmit or receive signal (+ differential) 6 VDDA_3.3 P 7 AGND GND 8 ISET O Set physical transmit output current. Pull-down this pin with an 11.8kΩ 1% resistor to ground. 9 VDDA_1.
KSZ8873MLL/FLL/RLL TABLE 2-1: Pin Number SIGNALS (CONTINUED) Type Note 2-1 Pin Name Description 26 SMTXC3/ REFCLKI_3 I/O MLL/FLL: Switch MII transmit clock (MII mode only) Output in PHY MII mode and SNI mode Input in MAC MII and RMII mode. RLL: Reference clock input Note: Pull-down by resistor is needed if internal reference clock is used in RLL by register 198 bit 3. 27 SMTXER3/ MII_LINK_3 Ipd Switch MII transmit error in MII mode 0= MII link indicator from host in MII PHY mode.
KSZ8873MLL/FLL/RLL TABLE 2-1: Pin Number SIGNALS (CONTINUED) Pin Name Type Note 2-1 36 SMRXC3/NC I/O 37 GND GND 38 VDDC P 39 SPIQ Ipu/O Description MLL/FLL: Switch MII receive clock. Output in PHY MII mode Input in MAC MII mode RLL: No Connection. Digital ground 1.8V digital core power input from VDDCO (pin 56). SPI slave mode: serial data output Note: an external pull-up is needed on this pin when it is in use.
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Pin Number Pin Name Type Note 2-1 51 P3SPD Ipd/O PU = force port 3 to 10BT PD = force port 3 to 100BT (default) 52 NC NC Unused pin. No external connection. 53 NC NC Unused pin. No external connection. 54 VDDIO P 55 GND GND 56 VDDCO P 57 NC NC 58 59 P1LED1 P1LED0 Description 3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well decoupling capacitors. Digital ground 1.8V core power voltage output (internal 1.
KSZ8873MLL/FLL/RLL TABLE 2-1: Pin Number SIGNALS (CONTINUED) Pin Name Type Note 2-1 Description Port 2 LED Indicators: Default: Speed (refer to register 195 bit[5:4]) Strap option: Serial bus configuration Port 2 LED Indicators: Default: Link/Act. (refer to register 195 bit[5:4]) Strap option: Serial bus configuration Serial bus configuration pins to select mode of access to KSZ8873MLL/FLL/ RLL internal registers.
KSZ8873MLL/FLL/RLL TABLE 2-1: SIGNALS (CONTINUED) Pin Number Pin Name Type Note 2-1 62 RSTN Ipu 63 FXSD1 I MLL/RLL: Connect to analog ground by pull-down resistor FLL: Fiber signal detect 64 VDDA_1.8 P 1.8V analog VDD input power supply from VDDCO (Pin 56) through external ferrite bead and capacitors.
KSZ8873MLL/FLL/RLL 3.0 FUNCTIONAL DESCRIPTION The KSZ8873MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated Layer 2 managed switch. The KSZ8873MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the host processor has complete control of the KSZ8873MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or I2C bus.
KSZ8873MLL/FLL/RLL 3.1.6 100BASE-FX SIGNAL DETECTION In 100BASE-FX operation, FXSD (fiber signal detect), input pins 15 and 63, is usually connected to the fiber transceiver SD (signal detect) output pin. The fiber signal threshold can be selected by register 192 bit 7 and 6 respectively for port 1 and port 2. When FXSD is less than the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the fiber signal is detected.
KSZ8873MLL/FLL/RLL 3.1.10.1 Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts a typical straight cable connection between a NIC card (MDI) and a switch or hub (MDI-X).
KSZ8873MLL/FLL/RLL 3.1.10.2 Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
KSZ8873MLL/FLL/RLL FIGURE 3-3: AUTO-NEGOTIATION AND PARALLEL OPERATION START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.1.12 LINKMD® CABLE DIAGNOSTICS KSZ8873MLL/FLL/RLL supports LinkMD.
KSZ8873MLL/FLL/RLL 2. 3. 4. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete. Read cable diagnostic test results in register 42, bits [6:5].
KSZ8873MLL/FLL/RLL During the normal operation mode, the host CPU can set the bit[1:0] in register 195 to transit the current normal operation mode to any one of the other three power management operation modes. 3.2.2 POWER SAVING MODE The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in register 195.
KSZ8873MLL/FLL/RLL 3.3.2 LEARNING The internal lookup engine updates its table with a new entry if the following conditions are met: • The received packet's source address (SA) does not exist in the lookup table. • The received packet is good; the packet has no receiving errors, and is of legal length. The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full, the last entry of the table is deleted to make room for the new entry. 3.3.
KSZ8873MLL/FLL/RLL FIGURE 3-4: DESTINATION ADDRESS LOOKUP FLOW CHART, STAGE 1 Start PTF1= NULL NO VLAN ID Valid? - Search VLAN table - Ingress VLAN filtering - Discard NPVID check YES Search complete. Get PTF1 from Static MAC Table FOUND Search Static Table This search is based on DA or DA+FID NOT FOUND Search complete. Get PTF1 from Dynamic MAC Table FOUND Dynamic Table Search This search is based on DA+FID NOT FOUND Search complete.
KSZ8873MLL/FLL/RLL FIGURE 3-5: DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2 PTF1 Spanning Tree Process - Check receiving port's receive enable bit - Check destination port's transmit enable bit - Check whether packets are special (BPDU or specified) IGMP Process - Applied to MAC #1 and MAC #2 - MAC #3 is reserved for microprocessor - IGMP will be forwarded to port 3 Port Mirror Process - RX Mirror - TX Mirror - RX or TX Mirror - RX and TX Mirror Port VLAN Membership Check PTF2 The KSZ8873ML
KSZ8873MLL/FLL/RLL 3.3.7.3 Late Collision If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. 3.3.7.4 Illegal Frames The KSZ8873MLL/FLL/RLL discards frames less than 64 bytes and can be programmed to accept frames up to1518 bytes, 1536 bytes, or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Because the KSZ8873MLL/FLL/RLL supports VLAN tags, the maximum sizing is adjusted when these tags are present. 3.3.7.
KSZ8873MLL/FLL/RLL 3.3.7.8 Port Individual MAC Address and Source Port Filtering The KSZ8873MLL/FLL/RLL provide individual MAC address for port 1 and port 2 respectively. They can be set at register 142-147 and 148-153. With this feature, the CPU connected to the port 3 can receive the packets from two internet subnets which has their own MAC address. The packet will be filtered if its source address matches the MAC address of port 1 or port 2 when the register 21 and 37 bit 6 is set to 1 respectively.
KSZ8873MLL/FLL/RLL • Uses a single 50 MHz clock reference (provided internally or externally). • Provides independent 2-bit wide (di-bit) transmit and receive data paths. • Contains two distinct groups of signals: one for transmission and the other for reception When EN_REFCLKO_3 is high, KSZ8873RLL will output a 50 MHz in REFCLKO_3. Register 198 bit[3] is used to select internal or external reference clock.
KSZ8873MLL/FLL/RLL TABLE 3-6: RMII SIGNAL DESCRIPTION (CONTINUED) RMII Signal Name Direction (with respect to PHY) Direction (with respect to MAC) RMII Signal Description KSZ8873RLL RMII Signal Direction TXD0 Input Output Transmit data bit 0 SMTXD30 (input) RX_ER Output Input (not required) Receive error (not used) — SMTXER3 (input) Connects to RX_ER signal of RMII PHY device — — — The KSZ8873RLL filters error frames and, thus, does not implement the RX_ER output signal.
KSZ8873MLL/FLL/RLL TABLE 3-8: MII MANAGEMENT FRAME FORMAT Preamble Start of Frame Read/ Write OP Code PHY Address Bits[4:0] REG Address Bits[4:0] TA Data Bits[15:0] Idle Read 32 1’s 01 10 AAAAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 AAAAA RRRRR 10 DDDDDDDD_DDDDDDDD Z 3.3.11 SERIAL MANAGEMENT INTERFACE (SMI) The SMI is the KSZ8873MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8873MLL/FLL/RLL configuration registers.
KSZ8873MLL/FLL/RLL 3.4.2 IEEE 802.1Q VLAN SUPPORT The KSZ8873MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q specification. KSZ8873MLL/FLL/RLL provides a 16-entries VLAN table that converts the 12-bits VLAN ID (VID) to the 4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is used for lookup.
KSZ8873MLL/FLL/RLL 3.4.5 802.1P-BASED PRIORITY For 802.1p-based priority, the KSZ8873MLL/FLL/RLL examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as specified by the registers 12 and 13. The “priority mapping” value is programmable. Figure 3-6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
KSZ8873MLL/FLL/RLL TABLE 3-12: SPANNING TREE STATES Disable State The port should not forward or receive any packets. Learning is disabled. Blocking State Only packets to the processor are forwarded. Learning is disabled. Listening State Only packets to and from the processor are forwarded. Learning is disabled. Learning State Only packets to and from the processor are forwarded. Learning is enabled. Forwarding State Packets are forwarded and received normally. Learning is enabled. 3.
KSZ8873MLL/FLL/RLL Learning state: only packets to and from the processor are forwarded. Learning is enabled. Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0.” Software action: The processor should program the static MAC table with the entries that it needs to receive (e.g., BPDU packets). The “overriding” bit should be set so that the switch will forward those specific packets to the processor.
KSZ8873MLL/FLL/RLL 3.8 IGMP Support For Internet Group Management Protocol (IGMP) support in layer 2, the KSZ8873MLL/FLL/RLL provides two components: IGMP snooping and IGMP send-back to the subscribed port. 3.8.1 IGMP SNOOPING The KSZ8873MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol version number = 0x2. 3.8.
KSZ8873MLL/FLL/RLL If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control will be triggered. As a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate.
KSZ8873MLL/FLL/RLL 5. 6. Place the EEPROM on the board and power up the board. Assert an active-low reset to the RSTN pin of the KSZ8873MLL/FLL/RLL. After reset is de-asserted, the KSZ8873MLL/FLL/RLL begins reading the configuration data from the EEPROM. The KSZ8873MLL/FLL/RLL checks that the first byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues.
KSZ8873MLL/FLL/RLL The following is a sample procedure for programming the KSZ8873MLL/FLL/RLL using the SPI bus: 1. At the board level, connect the KSZ8873MLL/FLL/RLL pins as follows: TABLE 3-14: 2. 3. 4. 5.
KSZ8873MLL/FLL/RLL FIGURE 3-10: SPI READ DATA CYCLE SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 SPIQ D7 READ COMMAND FIGURE 3-11: D6 D5 READ ADDRESS D4 D3 D2 D1 D0 READ DATA SPI MULTIPLE WRITE SPIS_N SPIC SPID X 0 0 0 0 0 0 1 0 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 SPIQ WRITE COMMAND WRITE ADDRESS Byte 1 SPIS_N SPIC SPID D7 D6 D5 D4 D4 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 SPI
KSZ8873MLL/FLL/RLL FIGURE 3-12: SPI MULTIPLE READ SPIS_N SPIC SPID X 0 0 0 0 0 0 1 1 A7 A6 A5 A4 A3 A2 A1 SPIQ READ COMMAND A0 X X X X X X X X D7 D6 D5 D4 D3 D2 D1 D0 READ ADDRESS Byte 1 SPIS_N SPIC SPID X X X X X X X X X X X X X X X X X X X X X X X X SPIQ D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Byte 2 3.
KSZ8873MLL/FLL/RLL FIGURE 3-13: FAR-END LOOPBACK PATH RXP / RXM Originating PHY Port TXP / TXM PMD/PMA PCS MAC Switch MAC PCS PMD/PMA Loop Back PHY Port 3.13.2 NEAR-END (REMOTE) LOOPBACK Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of the KSZ8873MLL/FLL/RLL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx).
KSZ8873MLL/FLL/RLL 4.0 REGISTER DESCRIPTIONS 4.1 MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C, and SMI interfaces can also be used to access some of these registers. The latter three interfaces use a different mapping mechanism than the MIIM interface. The “PHYADs” by defaults are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2).
KSZ8873MLL/FLL/RLL 4.2 Register Descriptions TABLE 4-2: Bit REGISTER DESCRIPTIONS Name R/W Description Default Reference PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control 15 Soft Reset RO Not Supported 0 — 0 Reg. 29, bit 0 Reg. 45, bit 0 14 Loopback R/W 1 = Perform loopback, as indicated: Port 1 Loopback (reg.
KSZ8873MLL/FLL/RLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Bit Name R/W Description 11 10 Half Capable RO 1 = 10BASE-T half-duplex capable 0 = Not 10BASE-T half-duplex capable 10-7 Reserved RO — 6 Preamble Suppressed RO 5 AN Complete 4 Default 1 Reference Always 1 0000 — Not Supported 0 — RO 1 = Auto-negotiation complete 0 = Auto-negotiation not completed 0 Reg. 30, bit 6 Reg. 46, bit 6 Far-End Fault RO 1 = Far-end fault detected 0 = No far-end fault detected 0 Reg.
KSZ8873MLL/FLL/RLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Bit Name R/W Description 10 Pause RO Link partner pause capability 0 Reg. 30, bit 4 Reg. 46, bit 4 9 Reserved RO — 0 — 8 Adv 100 Full RO Link partner 100 full-duplex capability 0 Reg. 30, bit 3 Reg. 46, bit 3 7 Adv 100 Half RO Link partner 100 half-duplex capability 0 Reg. 30, bit 2 Reg. 46, bit 2 6 Adv 10 Full RO Link partner 10 full-duplex capability 0 Reg. 30, bit 1 Reg.
KSZ8873MLL/FLL/RLL TABLE 4-2: Bit 4.3 REGISTER DESCRIPTIONS (CONTINUED) Name R/W Description 0 Reg. 26, bit 1 Reg. 42, bit 1 0 — 1 Remote Loopback R/W 1 = Perform Remote loopback, as follows: Port 1 (reg. 26, bit 1 = ‘1’) Start: RXP1/RXM1 (port 1) Loopback: PMD/PMA of port 1’s PHY End: TXP1/TXM1 (port 1) Port 2 (reg.
KSZ8873MLL/FLL/RLL TABLE 4-5: ADVANCED CONTROL REGISTERS (CONTINUED) Register (Decimal) Register (Hex) 192 0xC0 4.
KSZ8873MLL/FLL/RLL TABLE 4-6: Bit GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default R/W 1 = will enable receive direction flow control feature. 0 = will not enable receive direction flow control feature. Switch will not react to any flow control (PAUSE) frame it receives. 1 0 4 IEEE 802.3x Receive Direction Flow Control Enable 3 Frame Length Field Check R/W 1 = will check frame length field in the IEEE packets.
KSZ8873MLL/FLL/RLL TABLE 4-6: Bit 0 GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default Reserved R/W Reserved Do not change the default value. 0 Register 5 (0x05): Global Control 3 7 802.1Q VLAN Enable R/W 1 = 802.1Q VLAN mode is turned on. VLAN table needs to set up before the operation. 0 = 802.1Q VLAN is disabled. 0 6 IGMP Snoop Enable on Switch MII Interface R/w 1 = IGMP snoop is enabled. All IGMP packets will be forwarded to the Switch MII port.
KSZ8873MLL/FLL/RLL TABLE 4-6: Bit 5 GLOBAL REGISTERS (0-15) (CONTINUED) Name Port 3 Flow Control Enable R/W Description Default R/W 1 = Enable full-duplex flow control on Switch port 3 MII interface. 0 = Disable full-duplex flow control on Switch port 3 MII interface. 1 Pin P1LED1 strap option. Pull- up(1): Enable flow control Pull-down(0): Disable flow control Note: P1LED1 has internal pullup. 4 Port 3 Speed Selection R/W 0 Pin P3SPD strap option.
KSZ8873MLL/FLL/RLL TABLE 4-6: Bit GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Default Register 11 (0x0B): Global Control 9 7-6 CPU Interface Clock Selection R/W 00 = 31.25 MHz supports SPI speed below 6 MHz 01 = 62.5 MHz supports SPI speed between 6 MHz to 12.5 MHz 10 = 125 MHz supports SPI speed above 12.5 MHz Note: Lower clock speed will save more power; It is better set to 31.25 MHz if SPI doesn’t request a high speed.
KSZ8873MLL/FLL/RLL TABLE 4-6: Bit 3 2-0 GLOBAL REGISTERS (0-15) (CONTINUED) Name R/W Description Reserved RO Reserved Do not change the default values. Unknown Packet Default Port R/W Default 0 Specify which port(s) to send packets with unknown destination MAC addresses. This feature is enabled by bit [7] of this register. Bit 2 stands for port 3. Bit 1 stands for port 2. Bit 0 stands for port 1. 111 A ‘1’ includes a port. A ‘0’ excludes a port.
KSZ8873MLL/FLL/RLL The following registers are used to enable features that are assigned on a per port basis. The register bit assignments are the same for all ports, but the address for each port is different, as indicated.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit 6 5 4 3 2-0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Receive Sniff Transmit Sniff Double Tag User Priority Ceiling Port VLAN Membership R/W Description Default R/W 1 = All packets received on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 = no receive monitoring 0 R/W 1 = All packets transmitted on the port will be marked as “monitored packets” and forwarded to the designated “sniffer port” 0 =
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description Default 2 Transmit Enable R/W 1 = enable packet transmission on the port 0 = disable packet transmission on the port Note: This bit is used for spanning tree support. 1 1 Receive Enable R/W 1 = enable packet reception on the port 0 = disable packet reception on the port Note: This bit is used for spanning tree support.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit 1 0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Count IFG Count Pre R/W Description Default R/W Count IFG bytes 1 = each frame’s minimum inter frame gap (IFG) bytes (12 per frame) are included in Ingress and Egress rate limiting calculations. 0 = IFG bytes are not counted. 0 R/W Count Preamble bytes 1 = each frame’s preamble bytes (8 per frame) are included in Ingress and Egress rate limiting calculations. 0 = preamble bytes are not counted.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) R/W Description Vct_result RO 00 = Normal condition 01 = Open condition detected in cable 10 = Short condition detected in cable 11 = Cable diagnostic test has failed 00 4 Vct_en R/W (SC) 1 = Enable cable diagnostic test. After VCT test has completed, this bit will be self-cleared. 0 = Indicate cable diagnostic test (if enabled) has completed and the status information is valid for read.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description Default 1 For port 1, P1DPX pin value during reset. For port 2, SMRXD31 pin value during reset. 5 Force Duplex R/W 1 = forced full-duplex if (1) AN is disabled or (2) AN is enabled, but failed. 0 = forced half-duplex if (1) AN is disabled or (2) AN is enabled but failed.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit 0 PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name Loopback R/W Description R/W 1 = perform loopback, as indicated: Port 1 Loopback (reg. 29, bit 0 = ‘1’) Start: RXP2/RXM2 (port 2) Loopback: PMD/PMA of port 1’s PHY End: TXP2/TXM2 (port 2) Port 2 Loopback (reg.
KSZ8873MLL/FLL/RLL TABLE 4-7: Bit PORT REGISTERS (REGISTERS 16 - 95) (CONTINUED) Name R/W Description 2 Operation Speed RO 1 = link speed is 100 Mbps 0 = link speed is 10 Mbps 0 1 Operation Duplex RO 1 = link duplex is full 0 = link duplex is half 0 0 Far-End Fault Default 0 Note: This bit is applicable to port 1 and port 2 for FLL part only.
KSZ8873MLL/FLL/RLL 4.5 Advanced Control Registers (Registers 96-198) The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit Differentiated Services Code Point (DSCP) register set that is used to determine priority from the Type of Service (TOS) field in the IP header. The most significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared against the corresponding bits in the DSCP register to determine the priority.
KSZ8873MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 5-4 DSCP[29:28] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0E. 00 3-2 DSCP[27:26] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x0D.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 103 (0x67): TOS Priority Control Register 7 7-6 DSCP[63:62] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1F. 00 5-4 DSCP[61:60] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x1E.
KSZ8873MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 1-0 DSCP[81:80] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x28. 00 Register 107 (0x6B): TOS Priority Control Register 11 7-6 DSCP[95:94] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x2F.
KSZ8873MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description Default 3-2 DSCP[115:114] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x39. 00 1-0 DSCP[113:112] R/W The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic Class value is 0x38.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default 00 00 3-2 Table Select R/W 00 = static MAC address table selected 01 = VLAN table selected 10 = dynamic MAC address table selected 11 = MIB counter selected 1-0 Indirect Address High R/W Bits [9:8] of indirect address Register 122 (0x7A): Indirect Access Control 1 7-0 Indirect Address Low R/W Bits [7:0] of indirect address.
KSZ8873MLL/FLL/RLL TABLE 4-9: ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Bit Name R/W Description 6-0 Q0 Egress Data Rate Limit R/W Egress data rate limit for priority 0 frames Egress traffic from this priority queue is shaped according to Table 4-8.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default 6 Reserved RO Reserved Do not change the default values. 0 5-0 Reserved RO Reserved Do not change the default values. 0x18 Register 172 (0xAC): PM Usage Flow Control Select Mode 2 7-6 Reserved RO Reserved Do not change the default values. 0 5-0 Reserved RO Reserved Do not change the default values.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 179 (0xB3): TXQ Split for Q3 in Port 2 7 6-0 Priority Select R/W 0 = enable straight priority with Reg 180/181/182 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first 1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 180/181/182 bits[7]=1. Reserved RO Reserved Do not change the default values.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default Register 186 (0xBA): TXQ Split for Q0 in Port 3 7 6-0 Priority Select R/W 0 = enable straight priority with Reg 183/184/185 bits[7]=0 and Reg 5 bit[3]=0 for higher priority first 1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with Reg 183/184/185 bits[7]=1. Reserved RO Reserved Do not change the default values.
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default 3 Insert SRC Port 2 PVID at Port 1 R/W 1= insert SRC port 2 PVID for untagged frame at egress port 1 0 2 Insert SRC Port 2 PVID at Port 3 R/W 1= insert SRC port 2 PVID for untagged frame at egress port 3 0 1 Insert SRC Port 3 PVID at Port 1 R/W 1= insert SRC port 3 PVID for untagged frame at egress port 1 0 0 Insert SRC Port 3 PVID at Port 2 R/W 1= insert SRC port
KSZ8873MLL/FLL/RLL TABLE 4-9: Bit ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED) Name R/W Description Default R/W This value is used to control the minimum period the no energy event has to be detected consecutively before the device enters the low power state when the ED mode is on. The unit is 20 ms. The default go_sleep time is 1.6 seconds.
KSZ8873MLL/FLL/RLL Examples: 1. Static Address Table Read (Read the 2nd Entry) Write to reg. 121 (0x79) with 0x10 // Read static table selected Write to reg. 122 (0x7A) with 0x01 // Trigger the read operation Then, Read reg. 124 (0x7C), static table bits [57:56] Read reg. 125 (0x7D), static table bits [55:48] Read reg. 126 (0x7E), static table bits [47:40] Read reg. 127 (0x7F), static table bits [39:32] Read reg. 128 (0x80), static table bits [31:24] Read reg.
KSZ8873MLL/FLL/RLL and FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be broadcast to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned. Examples: 1. VLAN Table Read (read the 3rd entry) Write to reg. 121 (0x79) with 0x14 // Read VLAN table selected Write to reg. 122 (0x7A) with 0x02 // Trigger the read operation Then, Read reg. 129 (0x81), VLAN table bits [19:16] Read reg.
KSZ8873MLL/FLL/RLL Read reg. 124 (0x7C), dynamic table bits [63:56] Read reg. 125 (0x7D), dynamic table bits [55:48] Read reg. 126 (0x7E), dynamic table bits [47:40] Read reg. 127 (0x7F), dynamic table bits [39:32] Read reg. 128 (0x80), dynamic table bits [31:24] Read reg. 129 (0x81), dynamic table bits [23:16] Read reg. 130 (0x82), dynamic table bits [15:8] Read reg. 131 (0x83), dynamic table bits [7:0] 4.9 Management Information Base (MIB) Counters The KSZ8873 provides 34 MIB counters per port.
KSZ8873MLL/FLL/RLL TABLE 4-14: Offset PORT 1’S “PER PORT” MIB COUNTERS INDIRECT MEMORY OFFSETS Counter Name Description 0xC RxMulticast Rx good multicast packets (not including MAC control frames, error multicast packets or valid broadcast packets) 0xD RxUnicast Rx good unicast packets 0xE Rx64Octets Total Rx packets (bad packets included) that were 64 octets in length 0xF Rx65to127Octets Total Rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 Rx128to255Octe
KSZ8873MLL/FLL/RLL TABLE 4-16: “ALL PORT DROPPED PACKET” MIB COUNTERS INDIRECT MEMORY OFFSETS Offset Counter Name 0x105 Port 3 RX Drop Packets Description RX packets dropped due to lack of resources Examples: 1. MIB Counter Read (Read port 1 “Rx64Octets” Counter) Write to reg. 121 (0x79) with 0x1c // Read MIB counters selected Write to reg. 122 (0x7A) with 0x0e // Trigger the read operation Then Read reg.
KSZ8873MLL/FLL/RLL 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (VDDA_1.8, VDDC) ....................................................................................................................................... –0.5V to +2.4V (VDDA_3.3, VDDIO) ...................................................................................................................................... –0.5V to +4.0V Input Voltage ........................................................
KSZ8873MLL/FLL/RLL 6.0 ELECTRICAL CHARACTERISTICS TA = 25°C. Specification is for packaged product only. Current consumption is for the single 3.3V supply device only and includes the 1.8V supply voltages (VDDA, VDDC) that are provided via power output pin 56 (VDDCO). Each PHY port’s transformer consumes an additional 45 mA at 3.3V for 100BASE-TX and 70 mA at 3.3V for 10BASET at full traffic. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max.
KSZ8873MLL/FLL/RLL TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Symbol Min. Typ. Max. Units Note Output Voltage Imbalance VIMB — — 2 % 100Ω termination across differential output Rise/Fall Time tr/tf 3 — 5 ns — Rise/Fall Time Imbalance — 0 — 0.5 ns — Duty Cycle Distortion — — — ±0.5 ns — Overshoot — — — 5 % — Output Jitter — — 0.7 1.
KSZ8873MLL/FLL/RLL 7.0 TIMING SPECIFICATIONS 7.1 EEPROM Timing FIGURE 7-1: EEPROM INTERFACE INPUT TIMING DIAGRAM ts1 tcyc1 th1 Receive Timing SCL SDA FIGURE 7-2: EEPROM INTERFACE OUTPUT TIMING DIAGRAM tcyc1 Transmit Timing SCL tov1 SDA TABLE 7-1: EEPROM TIMING PARAMETERS Symbol Parameter Min. Typ. Max. Units tcyc1 Clock cycle — 16384 — ns ts1 Setup time 20 — — ns th1 Hold time tov1 Output valid 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL 7.2 MAC Mode MII Timing FIGURE 7-3: MAC MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-4: MAC MODE MII TIMING - DATA TRANSMITTED TO MII TABLE 7-2: MAC MODE MII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc3 Clock cycle — 400/40 — ns ts3 Setup time 4 — — ns th3 Hold time 2 — — ns tov3 Output valid 7 11 16 ns DS00002348A-page 78 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL 7.3 PHY Mode MII Timing FIGURE 7-5: PHY MODE MII TIMING - DATA RECEIVED FROM MII FIGURE 7-6: PHY MODE MII TIMING - DATA TRANSMITTED TO MII TABLE 7-3: PHY MODE MII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc4 Clock cycle — 400/40 — ns ts4 Setup time 10 — — ns th4 Hold time 0 — — ns tov4 Output valid 18 — 19 ns 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL 7.4 RMII Timing FIGURE 7-7: RMII TIMING - DATA RECEIVED FROM RMII tcyc Transmit Timing REFCLK t1 t2 MTXD [1 :0 ] MTXEN FIGURE 7-8: RMII TIMING - DATA TRANSMITTED TO RMII Receive Timing tcyc REFCLK MRXD [1: 0] MRXDV t od TABLE 7-4: RMII TIMING PARAMETERS Parameter Description Min. Typ. Max.
KSZ8873MLL/FLL/RLL 7.5 I2C Slave Mode Timing FIGURE 7-9: I2C INPUT TIMING FIGURE 7-10: I2C START BIT TIMING FIGURE 7-11: I2C STOP BIT TIMING FIGURE 7-12: I2C OUTPUT TIMING 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL TABLE 7-5: I2C TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tcyc Clock cycle 400 — — ns ts Setup time 33 — HalfCycle ns 0 — — ns th Hold time ttbs Start bit setup time 33 — — ns ttbh Start bit hold time 33 — — ns tsbs Stop bit setup time 2 — — ns tsbh Stop bit hold time 33 — — ns tov Output valid 64 — 96 ns Note that data is only allowed to change during SCL low-time, except the start and stop bits.
KSZ8873MLL/FLL/RLL 7.6 SPI Input Timing FIGURE 7-13: SPI INPUT TIMING tSHSL SPIS_N tSLCH tCHSL tSHCH tCHSH SPIC tCHCL tDVCH tCHDX tCLCH LSB MSB SPID tDLDH tDHDL High Impedance SPIQ TABLE 7-6: SPI INPUT TIMING PARAMETERS Timing Parameter Description fC Min. Typ. Max.
KSZ8873MLL/FLL/RLL 7.7 SPI Output Timing FIGURE 7-14: SPI OUTPUT TIMING SPIS_N tCH SPIC tCLQV tCL tSHQZ tCLQX LSB SPIQ tQLQH tQHQL SPID TABLE 7-7: SPI OUTPUT TIMING Parameter Description Min. Typ. Max.
KSZ8873MLL/FLL/RLL 7.8 Auto-Negotiation Timing FIGURE 7-15: AUTO-NEGOTIATION TIMING Auto-Negotiation - Fast Link Pulse Timing FLP Burst FLP Burst TX+/TX- t FLPW t BTB Clock Pulse Data Pulse t PW t PW TX+/TX- Data Pulse Clock Pulse t CTD t CTC TABLE 7-8: AUTO-NEGOTIATION TIMING PARAMETERS Parameter Description tBTB FLP burst to FLP burst tFLPW FLP burst width — tPW Clock/Data pulse width — tCTD Clock pulse to data pulse 55.
KSZ8873MLL/FLL/RLL 7.9 MDC/MDIO Timing FIGURE 7-16: TABLE 7-9: MDC/MDIO TIMING MDC/MDIO TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tP MDC period — 400 — ns tMD1 MDIO (PHY Input) setup to rising edge of MDC 10 — — ns tMD2 MDIO (PHY Input) hold from rising edge of MDC 4 — — ns tMD3 MDIO (PHY Output) delay from rising edge of MDC — 222 — ns DS00002348A-page 86 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL 7.10 Reset Timing The KSZ8873MLL/FLL/RLL reset timing requirement is summarized in Figure 7-17 and Table 7-10. FIGURE 7-17: RESET TIMING SUPPLY VOLTAGES tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN TABLE 7-10: RESET TIMING PARAMETERS Parameter Description Min. Typ. Max.
KSZ8873MLL/FLL/RLL 8.0 RESET CIRCUIT Figure 8-1 shows a reset circuit recommended for powering up the KSZ8873MLL/FLL/RLL if reset is triggered only by the power supply. FIGURE 8-1: RECOMMENDED RESET CIRCUIT VCC D1: 1N4148 R 10k D1 KS8873 RST C 10μF Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8873MLL/ FLL/RLL device.
KSZ8873MLL/FLL/RLL 9.0 SELECTION OF ISOLATION TRANSFORMERS A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. Table 9-1 lists recommended transformer characteristics. TABLE 9-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions Turns Ratio 1 CT : 1 CT — Open-Circuit Inductance (min.) 350 µH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 µH 1 MHz (min.
KSZ8873MLL/FLL/RLL 10.0 PACKAGE OUTLINE FIGURE 10-1: Note: 64-LEAD LQFP 10 MM X 10 MM PACKAGE For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002348A-page 90 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry — Converted Micrel data sheet KSZ8873MLL/FLL/ RLL to Microchip DS00002348A. Minor text changes throughout. Table 4-7 Updated the port register status 1 bit [0] description. Add power data for using external 1.8V LDO. Table 3-5 Updated the note of the RMII interface operation DS00002348A (1-30-17) 2017 Microchip Technology Inc.
KSZ8873MLL/FLL/RLL THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ8873MLL/FLL/RLL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: XX PART NO. X X X X a) KSZ8873MLL Device Interface Package Supply Temperature Media Type Voltage Device: KSZ8873 Interface: M = MII R = RMII F = Fibre Package: L = 64-lead LQFP Supply Voltage: L = Single 3.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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