Datasheet

KSZ8863MLL/FLL/RLL
DS00002335B-page 8  2017 Microchip Technology Inc.
39 SPISN Ipd
SPI Slave mode: chip select (active-low)
When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is
held in a high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note: An external pull-up is needed on this pin when using SPI or MDC/
MDIO-MIIM/SMI mode.
40 VDDIO P
3.3V, 2.5V, or 1.8V digital V
DD
input power supply for IO with well decou-
pling capacitors
41 GND GND Digital ground
42 VDDCO P
1.8V core power voltage output (internal 1.8V LDO regulator output)
This 1.8V output pin provides power to both VDDA_1.8 and VDDC input
pins.
Note: Internally, 1.8V LDO regulator input comes from VDDIO. Do not con-
nect an external power supply to VDDCO pin. The ferrite bead is
requested between analog and digital 1.8V core power.
43 P1LED1 Ipu/O
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option: Force the speed on port 1 (P1SPD)
PU = Force port 1 to 100BT if P1ANEN = 0
PD = Force port 1 to 10BT if P1ANEN = 0
44 P1LED0 Ipd/O
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option: Enable auto-negotiation on port 1 (P1ANEN)
PU = Enable (better to pull up in design)
PD = Disable (default)
TABLE 2-1: SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note 2-1
Description