Datasheet
KSZ8863MLL/FLL/RLL
DS00002335B-page 70 2017 Microchip Technology Inc.
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c // Read MIB counters selected
Write to reg. 122 (0x7A) with 0x0e // Trigger the read operation
Then
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow
valid bit [30] // If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e // Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow
valid bit [30] // If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Write to reg. 121 (0x79) with 0x1d // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x00 // Trigger the read operation
Then
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
4.9.1 ADDITIONAL MIB COUNTER INFORMATION
“Per Port” MIB counters are designed as “read clear.” These counters are cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity;
therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3) x 8 x 200 = 260 ms, where there are 160
registers, 3 overheads, 8 clocks per access, at 5 MHz. In the heaviest condition, the counters overflow in 2 minutes. It
is recommended that the software reads all the counters at least every 30 seconds.
A high performance SPI master is also recommended to prevent counters overflow.