Datasheet
KSZ8863MLL/FLL/RLL
DS00002335B-page 6 2017 Microchip Technology Inc.
TABLE 2-1: SIGNALS
Pin
Number
Pin
Name
Type
Note 2-1
Description
1 RXM1 I/O Physical receive or transmit signal (– differential)
2 RXP1 I/O Physical receive or transmit signal (+ differential)
3 TXM1 I/O
Physical transmit or receive signal (– differential)
4 TXP1 I/O
Physical transmit or receive signal (+ differential)
5 VDDA_3.3 P
3.3V analog V
DD
6 ISET O
Set physical transmit output current.
Pull down this pin with an 11.8 k 1% resistor to ground.
7 VDDA_1.8 P
1.8V analog core power input from VDDCO (pin 42).
8 RXM2 I/O Physical receive or transmit signal (– differential)
9 RXP2 I/O Physical receive or transmit signal (+ differential)
10 AGND GND Analog ground
11 TXM2 I/O Physical transmit or receive signal (– differential)
12 TXP2 I/O Physical transmit or receive signal (+ differential)
13 NC NC
No connection
14 X1 I
25 MHz or 50 MHz crystal or oscillator clock connections.
Pins (X1 and X2) connect to a crystal. If an oscillator is used, X1 connects
to a 3.3V tolerant oscillator, and X2 is a NC.
Note: The clock is ±50 ppm for both crystal and oscillator. The clock should
be applied to X1 pin before the reset voltage goes high.
15 X2 O
16 SMTXEN3 Ipu Switch MII transmit enable
17
SMTXD33/
EN_REFCLKO_3
Ipu
MLL/FLL: Switch MII transmit data bit 3
RLL: Strap option: RMII mode Clock selection
PU = Enable REFCLKO_3 output
PD = Disable REFCLKO_3 output
18 SMTXD32 Ipu
Switch MII transmit data bit 2
RLL: Strap option: X1 pin Clock selection (for Rev A3 and behind A3)
PU = 25 MHz to X1 pin as clock source (default)
PD = 50 MHz to X1 pin as clock source to provide or receive 50 MHz RMII
reference clock for RLL part
19 SMTXD31 Ipu Switch MII/RMII transmit data bit 1
20 SMTXD30 Ipu Switch MII/RMII transmit data bit 0
21 GND GND Digital ground
22 VDDIO P
3.3V, 2.5V, or 1.8V digital V
DD
input power supply for IO with well decou-
pling capacitors
23
SMTXC3/
REFCLKI_3
I/O
MLL/FLL: Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
Input in MAC MII and RMII mode
RLL: Reference clock input
Note: Pull-down by resistor is needed if the internal reference clock is used
in RLL by register 198 bit 3.
24
SMTXER3/
MII_LINK_3
Ipd
Switch port 3 MII transmit error in MII mode
0 = MII link indicator from host in MII PHY mode
1 = No link on port 3 MII PHY mode and enable bypass mode