Datasheet
KSZ8863MLL/FLL/RLL
DS00002335B-page 34 2017 Microchip Technology Inc.
3.13.1 FAR-END LOOPBACK
Far-end loopback is conducted between KSZ8863MLL/FLL/RLL’s two PHY ports. The loopback is limited to few pack-
ages a time for diagnostic purpose and cannot support large traffic. The loopback path starts at the “Originating” PHY
port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating”
PHY port’s transmit outputs (TXP/TXM).
Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 0, bit [14] can be used to enable far-end loopback.
The far-end loopback path is illustrated in Figure 3-13.
3.13.2 NEAR-END (REMOTE) LOOPBACK
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of KSZ8863MLL/FLL/RLL. The loopback
path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends
at the PHY port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 31, bit [1] can be used to enable near-end loopback.
The near-end loopback paths are illustrated in Figure 3-14.
FIGURE 3-13: FAR-END LOOPBACK PATH
PMD/PMA
PCS
MAC
Switch
MAC
PCS
PMD/PMA
TXP /
TXM
RXP /
RXM
Originating
PHY Port
Loop Back
PHY Port