Datasheet
2017 Microchip Technology Inc. DS00002335B-page 31
KSZ8863MLL/FLL/RLL
6. Assert an active-low reset to the RSTN pin of KSZ8863MLL/FLL/RLL. After reset is deasserted, KSZ8863MLL/
FLL/RLL begins reading the configuration data from the EEPROM. KSZ8863MLL/FLL/RLL checks that the first
byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM
configuration access is denied and all other data sent from the EEPROM is ignored by KSZ8863MLL/FLL/RLL.
3.12.2 I
2
C SLAVE SERIAL BUS CONFIGURATION
In managed mode, KSZ8863MLL/FLL/RLL can be configured as an I
2
C Slave device. In this mode, an I
2
C Master
device (external controller or CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes Global registers, Port registers, Advanced Control registers, and indirect access to the
“Static MAC Table,” “VLAN Table,” “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly
accessed via registers 121 to 131.
In I
2
C Slave mode, KSZ8863MLL/FLL/RLL operates like other I
2
C Slave devices. Addressing the KSZ8863MLL/FLL/
RLL’s 8-bit registers is similar to addressing the Microchip AT24C02 EEPROM’s memory locations. Details of I
2
C read
or write operations and related timing information can be found in the AT24C02 data sheet.
Two fixed 8-bit device addresses are used to address KSZ8863MLL/FLL/RLL in I
2
C Slave mode: one for read operation
and the other for write operation. The addresses are as follows:
• 1011_1111 <read>
• 1011_1110 <write>
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL using the I
2
C Slave serial bus:
1. Enable I
2
C Slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED [1:0] to “01”.
2. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL device. Configure the desired register settings
in KSZ8863MLL/FLL/RLL using the I
2
C write operation.
3. Read back and verify the register settings in KSZ8863MLL/FLL/RLL using the I
2
C read operation.
Some of the configuration settings, such as “Aging Enable,” “Auto Negotiation Enable,” “Force Speed,” and “Power
down,” can be programmed after the switch has been started.
3.12.3 SPI SLAVE SERIAL BUS CONFIGURATION
In managed mode, KSZ8863MLL/FLL/RLL can be configured as an SPI slave device. In this mode, an SPI master
device (external controller or CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers.
Programming access includes Global registers, Port registers, Advanced Control registers, and indirect access to the
“Static MAC Table,” “VLAN Table,” “Dynamic MAC Table,” and “MIB Counters”. The tables and counters are indirectly
accessed via registers 121 to 131.
KSZ8863MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data
write. KSZ8863MLL/FLL/RLL also supports SPI multiple read and multiple write to expedite register read back and reg-
ister configuration, respectively.
SPI multiple read is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN input pin (SPI
Slave Select signal) low after a byte (a register) is read. The KSZ8863MLL/FLL/RLL internal address counter increments
automatically to the next byte (next register) after the read. The next byte at the next register address is shifted out onto
the KSZ8863MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI master device terminates it by
deasserting the SPISN signal to KSZ8863MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the master device continues to drive the KSZ8863MLL/FLL/RLL SPISN
input pin low after a byte (a register) is written. The KSZ8863MLL/FLL/RLL internal address counter increments auto-
matically to the next byte (next register) after the write. The next byte that is sent from the master device to the
KSZ8863MLL/FLL/RLL SDA input pin is written to the next register address. SPI multiple write continues until the SPI
master device terminates it by deasserting the SPISN signal to KSZ8863MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8863MLL/FLL/RLL internal address counter wraps back to register
address zero once the highest register address is reached. This feature allows all 198 KSZ8863MLL/FLL/RLL registers
to be read, or written with a single SPI command from any initial register address.
KSZ8863MLL/FLL/RLL can support SPI bus up to a maximum of 25 MHz. A high performance SPI master is recom-
mended to prevent internal counter overflow.
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL using the SPI bus:
1. At the board level, connect the KSZ8863MLL/FLL/RLL pins as follows (Ta b l e 3- 14 ):