Datasheet
KSZ8863MLL/FLL/RLL
DS00002335B-page 30 2017 Microchip Technology Inc.
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
is triggered. As a result of congestion, the actual egress rate may be dominated by flow control or dropping at the ingress
end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
3.11 Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded
in the static table, it is also not learned in the dynamic MAC table. KSZ8863MLL/FLL/RLL is then configured with the
option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in
register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in appli-
cations such as voice over Internet Protocol (VoIP).
3.12 Configuration Interface
KSZ8863MLL/FLL/RLL can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, KSZ8863MLL/FLL/RLL is typically programmed using an EEPROM. If no EEPROM is present,
KSZ8863MLL/FLL/RLL is configured using its default register settings. Some default settings are configured via strap-
in pin options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
3.12.1 I
2
C MASTER SERIAL BUS CONFIGURATION
With an additional I
2
C (“2-wire”) EEPROM, KSZ8863MLL/FLL/RLL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For the KSZ8863MLL/FLL/RLL I
2
C Master configuration, the EEPROM stores the configuration data for register 0 to
register 198 (as defined in the KSZ8863MLL/FLL/RLL register map) with the exception of the “Read Only” status regis-
ters. After the deassertion of reset, KSZ8863MLL/FLL/RLL sequentially reads in the configuration data for all 199 reg-
isters, starting from register 0.
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL with a pre-configured EEPROM:
1. Connect KSZ8863MLL/FLL/RLL to the EEPROM by joining the SCL and SDA signals of the respective devices.
2. Enable I
2
C Master mode by setting the KSZ8863MLL/FLL/RLL strap-in pins, P2LED [1:0] to “00”.
3. Check to ensure that the KSZ8863MLL/FLL/RLL reset signal input (RSTN) is properly connected to the external
reset source at the board level.
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
FIGURE 3-8: EEPROM CONFIGURATION TIMING DIAGRAM
....
....
....
RST_N
SCL
SDA
t
prgm
<15 ms