Datasheet

KSZ8863MLL/FLL/RLL
DS00002335B-page 22 2017 Microchip Technology Inc.
Provides independent 2-bit wide (di-bit) transmit and receive data paths
Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8863RLL outputs a 50 MHz in REFCLKO_3. Register 198 bit [3] is used to select
the internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL is
provided by KSZ8863RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the clock
provides to KSZ8863RLL via REFCLKI_3.
If KSZ8863RLL does not provide the reference clock, this 50 MHz reference clock with divide-by-2 (25 MHz) has to be
used in X1 pin instead of the 25 MHz crystal, since the clock skew of these two clock sources impacts the RMII timing
before Rev A3 part. The Rev A3 part can connect the external 50 MHz reference clock to X1 pin and SMTXC3/REF-
CLKI_3 pins directly with strap pins of pin 17 SMTXD33/EN_REFCLKO_3 and pin 18 SMTXD32 to be pulled down.
The RMII provided by KSZ8863RLL is connected to the device’s third MAC and complies with the RMII Specification.
Table 3-6 describes the signals that the RMII bus is using. Refer to RMII Specification for full detail on the signal descrip-
tion.
TABLE 3-5: RMII CLOCK SETTING
Reg. 198
Bit [3]
Pin 17 SMTXD33/
EN_REFCLKO_3
Internal pull-up
Pin 18 SMTXD32
Internal pull-up
(For Rev A3)
Clock Source Note
0
0
(pull down by 1k)
0
(pull down by 1k)
External 50 MHz OSC input to
SMTXC3 /REFCLKI_3 and X1
pin directly
EN_REFCLKO_3 = 0 to
disable REFCLKO_3 for
better EMI
01
0
(pull down by 1k)
50 MHz on X1 pin is as clock
source. REFCLKO_3 Output
is Feedback to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
enable REFCLKO_3
01 1
25 MHz on X1 pin is as clock
source.
REFCLKO_3 Output is
connected to REFCLKI_3
externally
EN_REFCLKO_3 = 1 to
enable REFCLKO_3
11 0
50 MHz on X1 pin, 50 MHz
RMII Clock goes to SMTXC3/
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
EN_REFCLKO_3 = 1 to
enable REFCLKO_3 and no
feedback to REFCLKI_3
11 1
25 MHz on X1 pin, 50 MHz
RMII Clock goes to SMTXC3/
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
EN_REFCLKO_3 = 1 to
enable REFCLKO_3 and no
feedback to REFCLKI_3
TABLE 3-6: RMII SIGNAL DESCRIPTION
RMII Signal Name
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8863RLL RMII
Signal Direction
REF_CLK Input Input or Output
Synchronous 50 MHz
clock reference for
receive, transmit, and
control interface
REFCLKI_3 (input)
CRS_DV Output Input
Carrier sense/
Receive data valid
SMRXDV3 (output)
RXD1 Output Input Receive data bit 1 SMRXD31 (output)
RXD0 Output Input Receive data bit 0 SMRXD30 (output)
TX_EN Input Output Transmit enable SMTXEN3 (input)
TXD1 Input Output Transmit data bit 1 SMTXD31 (input)