Datasheet
2017 Microchip Technology Inc. DS00002335B-page 21
KSZ8863MLL/FLL/RLL
3.3.7.8 Port Individual MAC Address and Source Port Filtering
KSZ8863MLL/FLL/RLL provides individual MAC address for port 1 and port 2. They can be set at registers 142-147 and
148-153. The packet is filtered if its source address matches the MAC address of port 1 or port 2 when register 21 and
37 bit 6 is set to 1, respectively. For example, the packet is dropped after it completes the loop of a ring network.
3.3.8 MII INTERFACE OPERATION
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by KSZ8863MLL/FLL is connected to the
device’s third MAC; the MII default is PHY mode and can be set to MAC mode with the register 53 bit 7. The interface
contains two distinct groups of signals: one for transmission and the other for reception. Ta b l e 3 - 4 describes the signals
used by the MII bus.
The MII operates in either PHY mode or MAC mode. The data interface is nibble-wide and runs at ¼ the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during trans-
mission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For
half-duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
KSZ8863MLL/FLL does not provide the MRXER signal for PHY mode operation, and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Because the switch filters error frames, these MII error signals are not used by
KSZ8863MLL/FLL. So, for PHY mode operation, if the device interfacing with KSZ8863MLL/FLL has an MRXER input
pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with KSZ8863MLL/FLL has an
MTXER input pin, it also needs to be tied low.
KSZ8863MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status.
If the host is powered down, pin MII_LINK goes to high. In this case, no new ingress frames from port 1 or port 2 are
sent out through port 3, and the frames for port 3 already in packet memory are flushed out.
3.3.9 RMII INTERFACE OPERATION
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Ports 10 Mbps and 100 Mbps data rates
• Uses a single 50 MHz clock reference (provided internally or externally)
TABLE 3-4: MII SIGNALS
PHY Mode Connections
Pin Description
MAC Mode Connections
External MAC
Controller Signals
KSZ8863MLL/FLL
PHY Signals
External PHY
Signals
KSZ8863MLL/FLL
MAC Signals
MTXEN SMTXEN3 Transmit Enable MTXEN SMRXDV3
MTXER SMTXER3 Transmit Error MTXER (NOT USED)
MTXD3 SMTXD33 Transmit Data Bit 3 MTXD3 SMRXD33
MTXD2 SMTXD32 Transmit Data Bit 2 MTXD2 SMRXD32
MTXD1 SMTXD31 Transmit Data Bit 1 MTXD1 SMRXD31
MTXD0 SMTXD30 Transmit Data Bit 0 MTXD0 SMRXD30
MTXC SMTXC3 Transmit Clock MTXC SMRXC3
MCOL SCOL3 Collision Detection MCOL SCOL3
MCRS SCRS3 Carrier Sense MCRS SCRS3
MRXDV SMRXDV3 Receive Data Valid MRXDV SMTXEN3
MRXER (NOT USED) Receive Error MRXER SMTXER3
MRXD3 SMRXD33 Receive Data Bit 3 MRXD3 SMTXD33
MRXD2 SMRXD32 Receive Data Bit 2 MRXD2 SMTXD32
MRXD1 SMRXD31 Receive Data Bit 1 MRXD1 SMTXD31
MRXD0 SMRXD30 Receive Data Bit 0 MRXD0 SMTXD30
MRXC SMRXC3 Receive Clock MRXC SMTXC3