Datasheet

KSZ8863MLL/FLL/RLL
DS00002335B-page 16 2017 Microchip Technology Inc.
2. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing.
3. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete.
4. Read cable diagnostic test results in register 42, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when KSZ8863MLL/FLL/RLL is unable to shut down the link partner. In this instance,
the test is not run because it is impossible for KSZ8863MLL/FLL/RLL to determine if the detected signal is a reflection
of the signal generated or a signal from another source.
5. Get the distance to fault by concatenating register 42, bit [0] and register 43, bits [7:0]; and multiplying the result
by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
Concatenated values of registers 42 and 43 are converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that
varies significantly from the norm.
3.2 Power Management
KSZ8863MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to
ensure low-power dissipation during device idle periods. There are five operation modes under the power management
function, which is controlled by two bits in register 195 (0xC3) and one bit in register 29 (0x1D), 45(0x2D) as shown
below:
Register 195 bit [1:0] = 00 Normal Operation Mode
Register 195 bit [1:0] = 01 Energy Detect Mode
Register 195 bit [1:0] = 10 Soft Power Down Mode
Register 195 bit [1:0] = 11 Power Saving Mode
Register 29, 45 bit 3 = 1 Port Based Power Down Mode
Table 3-3 indicates all internal function blocks status under four different power management operation modes.
3.2.1 NORMAL OPERATION MODE
This is the default setting bit [1:0] = 00 in register 195 after the chip power-up or hardware reset. When KSZ8863MLL/
FLL/RLL is in this normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is
ready for CPU read or write.
TABLE 3-3: INTERNAL FUNCTION BLOCK STATUS
KSZ8863MLL/FLL/RLL
Function Blocks
Power Management Operation Modes
Normal Mode
Power Saving
Mode
Energy Detect
Mode
Soft Power Down
Mode
Internal PLL Clock Enabled Enabled Disabled Disabled
Tx/Rx PHY Enabled
Rx unused block
disabled
Energy detect at Rx Disabled
MAC Enabled Enabled Disabled Disabled
Host Interface Enabled Enabled Disabled Disabled
DDis cetan
·
to cable fault in meters0.4 Register 26 bit [0] Register 27 bits [7:0]=