Datasheet

KSZ8863MLL/FLL/RLL

DS00002335B-page 12  2017 Microchip Technology Inc.

3.1.6 100BASE-FX SIGNAL DETECTION

In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (sig-

nal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for port 1. When FXSD is less than

the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the

fiber signal is detected.

Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD input pin is tied high

to force 100BASE-FX mode.

100BASE-FX signal detection is summarized in Table 3-1:

To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage

swing to match the FXSD pin’s input voltage threshold.

3.1.7 100BASE-FX FAR-END FAULT

A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The

KSZ8863FLL detects a FEF when its FXSD input is below the Fiber Signal Threshold. When a FEF is detected,

KSZ8863FLL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period

between frames. By default, FEF is enabled.

3.1.8 10BASE-T TRANSMIT

The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.

They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents

are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.

3.1.9 10BASE-T RECEIVE

On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit

and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into

clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to

prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit,

the PLL locks onto the incoming signal and KSZ8863MLL/FLL/RLL decodes a data frame. The receiver clock is main-

tained active during idle periods in between data reception.

3.1.10 MDI/MDI-X AUTO CROSSOVER

To eliminate the need for crossover cables between similar devices, KSZ8863MLL/FLL/RLL supports HP Auto MDI/

MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.

The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for

the KSZ8863MLL/FLL/RLL device. This feature is extremely useful when end users are unaware of cable types, and

also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the

port control registers, or MIIM PHY registers.

The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in Ta b l e 3-2 .

TABLE 3-1: FX SIGNAL THRESHOLD

12.0V

01.2V

TABLE 3-2: MDI/MDI-X PIN DEFINITIONS

MDI MDI-X

RJ-45 Pins Signals RJ-45 Pins Signals

1 TD+ 1 RD+

2TD–2RD–

3 RD+ 3 TD+

6 RD– 6 TD–