Datasheet

 2016-2017 Microchip Technology Inc. DS00002112B-page 99
KSZ8795CLX
7LPI
Terminated
By Input Traf-
fic Enable
1 = LPI request will be stopped if input traffic is
detected.
0 = LPI request won’t be stopped by input traffic.
R/W 0
6 - 0 Reserved — RO 0x10
EEE Global Register 1
Global Empty TXQ to LPI Wait Time Control Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x32 (Bits[15:8]), 0x33 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 0 Empty TXQ
to LPI Wait
Time
This register specifies the time that the LPI request
will be generated after a TXQ has been empty
exceeds this configured time. This is only valid
when EEE 100BT is enabled. This setting will apply
to all the ports. The unit is 1.3 ms. The default
value is 1.3s (range from 1.3 ms to 86 seconds)
R/W 0x10
EEE Global Register 2
Global EEE PCS DIAGNOSTIC Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x34(Bits[15:8]), 0x35 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 12 Reserved — RO 0x6
11 - 8 Reserved — RO 0x8
7 - 4 Reserved — RO 0x0
3 Port 4 Next
Page Enable
1 = Enable next page exchange during Auto-Nego-
tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
R/W 1
2 Port 3 Next
Page Enable
1 = Enable next page exchange during Auto-Nego-
tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
R/W 1
1 Port 2 Next
Page Enable
1 = Enable next page exchange during Auto-Nego-
tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
R/W 1
0 Port 1 Next
Page Enable
1 = Enable next page exchange during Auto-Nego-
tiation.
0 = Skip next page exchange during Auto-Negotia-
tion.
R/W 1
EEE Global Register 3
Global EEE Minimum LPI cycles before back to Idle Control Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x36 (Bits[15:8], 0x37 (Bits[7:0])
Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
15 - 0 Reserved — RO 0x0000
TABLE 4-24: EEE GLOBAL REGISTERS (CONTINUED)
Address Name Description Mode Default