Datasheet
2016-2017 Microchip Technology Inc. DS00002112B-page 95
KSZ8795CLX
4 - 0 FORWARD
[4:0]
Port Map
Each bit indicates forwarding decision of one port.
Bit[0] = Port 1
Bit[1] = Port 2
Bit[2] = Port 3
Bit[3] = Port 4
Bit[4] = Port 5
When MD = 01 and ENB = 00,
Bit[4] is used as count unit:
0 = µs
1 = ms
Bit[3] is used to select count modes:
0 = count down in the 11-bit counter from an
assigned value in the Action field PM, P, RPE, RP,
and MM, an interrupt will be generated when
expired.
1 = count up in the 11-bit counter for every matched
packet received up to reach an assigned value in
the Action field PM, P, RPE, RP and MM, and then
an interrupt will be generated.
Note: See ENB field description for detail.
R/W —
Port_ACL_C
ACL Port Register 12 (0x0C)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x0C to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Processing Field
7 - 0 RULESET
[15:8]
Rule Set
Each bit indicates this entry in bits 0 to 16, total 16
entries of the rule list can be assigned for the rule
set to be used in the rules cascade per port.
R/W 00000000
Port_ACL_D
ACL Port Register 13 (0x0D)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x0D to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Processing Field
7 - 0 RULESET
[7:0]
Rule Set
Each bit indicates this entry in bits 0 to 16, total 16
entries of the rule list can be assigned for the rule
set to be used in the rules cascade per port.
R/W 00000000
TABLE 4-22: TEMPORAL STORAGE FOR 14 BYTES ACL RULES
Address Name Description Mode Default
Port_ACL_BYTE_ENB_MSB
ACL Port Register 14 (0x10)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, and 4.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x10 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
7 - 6 Reserved — RO 00
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)
Address Name Description Mode Default