Datasheet

KSZ8795CLX
DS00002112B-page 92  2016-2017 Microchip Technology Inc.
Port_ACL_7
ACL Port Register 7 (0x07)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7 - 0 IP_Mask
[23:16]
IP Mask R/W 00000000
Port_ACL_8
ACL Port Register 8 (0x08)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x08 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7 - 0 IP_Mask
[15:8]
IP Mask R/W 00000000
Port_ACL_9
ACL Port Register 9 (0x09)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 3
7 - 0 IP_Mask
[7:0]
IP Mask R/W 00000000
Note: Layer 2, Layer 3, and Layer 4 in matching field should be in different entries. Same layer should be in same
entry.
Port_ACL_2
ACL Port Register 2 (0x02)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x02 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 0 MAX Port
[15:8]
For range of TCP port number or sequence num-
ber matching
R/W 00000000
Port_ACL_3
ACL Port Register 3 (0x03)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 0 MIN Port
[7:0]
For range of TCP port number or sequence num-
ber matching
R/W 00000000
Port_ACL_4
ACL Port Register 4 (0x04)
Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5.
Reg. 111 (0x6F) Bits[7:0] = Offset 0x04 to access the Indirect Byte Register 0xA0.
Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
Matching Fields for Layer 4
7 - 3 Reserved — RO 00000
TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED)
Address Name Description Mode Default