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ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)5-Port Managed Ethernet Switch Ethernet/SPI/MAC/PHY/MII/RMII/RGMII/GMII LQFP-80
71727374757677787980
KSZ8795CLX
DS00002112B-page 74 2016-2017 Microchip Technology Inc.
TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1)
Address Name Description Mode Default
Register 176 (0xB0): Port 1 Control 12
Register 192 (0xC0): Port 2 Control 12
Register 208 (0xD0): Port 3 Control 12
Register 224 (0xE0): Port 4 Control 12
Register 240 (0xF0): Port 5 Control 12
7 Reserved — RO 1
6 Pass All
Frames
Port-based enable to pass all frames
1 = Enable
0 = Disable
Note: This is used in the port mirroring with
RX sniff only.
R/W 0
5 -4 Reserved — RO 00
3 Insert Source
Port PVID for
Untagged
Packet Desti-
nation to
Highest
Egress Port
Register 176: Insert source Port 1 PVID for
untagged frame at egress Port 5
Register 192: Insert source Port 2 PVID for
untagged frame at egress Port 5
Register 208: Insert source Port 3 PVID for
untagged frame at egress Port 5
Register 224: Insert source Port 4 PVID for
untagged frame at egress Port 5
Register 240: Insert source Port 5 PVID for
untagged frame at egress Port 4
Note: Enabled by the Register 135 Bit[2].
R/W 0
2 Insert Source
Port PVID for
Untagged
Packet Desti-
nation to
Second
Highest
Egress Port
Register 176: Insert source Port 1 PVID for
untagged frame at egress Port 4
Register 192: Insert source Port 2 PVID for
untagged frame at egress Port 4
Register 208: Insert source Port 3 PVID for
untagged frame at egress Port 4
Register 224: Insert source Port 4 PVID for
untagged frame at egress Port 3
Register 240: Insert source Port 5 PVID for
untagged frame at egress Port 3
Note: Enabled by the Register 135 Bit[2].
R/W 0
1 Insert Source
Port PVID for
Untagged
Packet Desti-
nation to
Second Low-
est Egress
Port
Register 176: Insert source Port 1 PVID for
untagged frame at egress Port 3
Register 192: Insert source Port 2 PVID for
untagged frame at egress Port 3
Register 208: Insert source Port 3 PVID for
untagged frame at egress Port 2
Register 224: Insert source Port 4 PVID for
untagged frame at egress Port 2
Register 240: Insert source Port 5 PVID for
untagged frame at egress Port 2
Note: Enabled by the Register 135 Bit[2].
R/W 0