Datasheet

KSZ8795CLX
DS00002112B-page 64  2016-2017 Microchip Technology Inc.
4.3 Advanced Control Registers
Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in
MAC pause control frames.
Use Registers 110 and 111 to read or write data to the static MAC address table, VLAN table, dynamic address table,
PME registers, ACL tables, EEE registers and the MIB counters.
TABLE 4-5: ADVANCED CONTROL REGISTERS 104 - 109
Address Name Description Mode Default
Register 104 (0x68): MAC Address Register 0
7 - 0 MACA[47:40] — R/W 0x00
Register 105 (0x69): MAC Address Register 1
7 - 0 MACA[39:32] — R/W 0x10
Register 106 (0x6A): MAC Address Register 2
7 - 0 MACA[31:24] — R/W 0xA1
Register 107 (0x6B): MAC Address Register 3
7 - 0 MACA[23:16] — R/W 0xff
Register 108 (0x6C): MAC Address Register 4
7 - 0 MACA[15:8] — R/W 0xff
Register 109 (0X6D): MAC Address Register 5
7 - 0 MACA[7:0] — R/W 0xff
TABLE 4-6: ADVANCED CONTROL REGISTERS 110 - 111
Address Name Description Mode Default
Register 110 (0x6E): Indirect Access Control 0
7 - 5 EEE/ACL/
PME Indirect
Register
Function
Select
000 = Indirect mode is used for table select in bits
[3:2]. While these bits are not equal 000, bits [3:2]
are used for 2 additional MSB address bits.
001 = Global and Port base EEE registers are
selected, port count is specified in 4 MSB indirect
address bits and 8 bits register pointer is specified
in 8 LSB indirect address bits.
010 = Port-base ACL registers are selected, Port
count is specified in 4 MSB indirect address bits
and register pointer is specified in 8 LSB indirect
address bits.
011 = Reserved
100 = PME control registers are selected.
101 = Reserved
R/W 000
4 Read High
Write Low
1 = Read cycle.
0 = Write cycle.
R/W 0