Datasheet

 2016-2017 Microchip Technology Inc. DS00002112B-page 59
KSZ8795CLX
2 GMII/MII Mode Select Port 5 GMAC5 SW5-GMII/MII Mode Select
1 = GMII/MII is in GMAC/MAC mode
(Default).
0 = GMII/MII is in GPHY/PHY mode.
Strap-in option: LED2_1
PU = GMII/MII is in GMAC/MAC mode. (Default)
PD = GMII/MII is in GPHY/PHY mode.
Note: When set GMAC5 SW5-GMII to GPHY
mode, the CRS and COL pins will
change from the input to output.
When set SW5-MII to PHY mode, the CRS, COL,
RXC and TXC pins will change from the input to
output.
R/W 1
1  0 Interface Mode Select
Note: This is for
port 5 SW5-
GMII/RGMII/
MII/RMII
These bits select the interface type and mode for
Switch Port 5 (SW5).
Port 5 Mode Select:
00 = MII
01 = RMII
10 = GMII
11 = RGMII.
Strap-in option: LED3[1:0]
00 = MII
01 = RMII
10 = GMII
11 = RGMII (Default)
Note: These pins have internal pull-ups.
R/W 11
Register 23 (0x17): Port 1 Control 7
Register 39 (0x27): Port 2 Control 7
Register 55 (0x37): Port 3 Control 7
Register 71 (0x47): Port 4 Control 7
Register 87 (0x57): Reserved
(Note 4-1)
7  6 Reserved N/A Don’t Change. RO 00
5  4 Advertised_Flow_Con-
trol _Capability
These bits indicate that the KSZ8795CLX has
implemented both the optional MAC control sub-
layer and the PAUSE function as specified in IEEE
Clause 31 and Annex 31B for full duplex operation
independent of rate and medium.
00 = No pause
01 = Symmetric PAUSE
10 = Asymmetric PAUSE toward link partner
toward link partner
11 = Both Symmetric PAUSE and Asymmetric
PAUSE toward local devices
Bit[5] indicates that asymmetric PAUSE is sup-
ported. The value of Bit[4] when Bit[5] is set indi-
cates the direction of the PAUSE frames that are
supported for flow across the link. Asymmetric
PAUSE configuration results in independent
enabling of the PAUSE receive and PAUSE trans-
mit functions as defined by IEEE Annex 31B.
R/W 11
TABLE 4-4: PORT REGISTERS (CONTINUED)
Address Name Description Mode Default