Datasheet

KSZ8795CLX
DS00002112B-page 58  2016-2017 Microchip Technology Inc.
6 Is_1Gbps 1 = 1Gbps is chosen for Port 5 in GMII/RGMII
mode.
0 = 10/100 Mbps is chosen for Port 5 in GMII/
RGMII mode.
Strap-in option: LED1_0
PU = 1Gbps in SW5-GMII/RGMII mode (Default)
PD = 10/100 Mbps in SW5-GMII/RGMII mode
Note: This pin has an internal pull-up.
Use Bit[4] of the Register 6, Global Control 4 to set
for 10 or 100 speed in 10/100 Mbps mode.
R/W 1
5 Reserved N/A Don’t change. RO 1
4 RGMII Internal Delay (ID)
Ingress Enable
Enable Ingress RGMII-ID Mode
1 = Ingress RGMII-ID enabled. An internal
delay is added to ingress clock input.
0 = No delay is added, only clock to data
skew applied.
Note: If RGMII connection partner transmit
data to clock skew is in standard spec
±0.5 ns without delay inserted on PCB,
then set bit [4] =’1’ will enable an
ingress delay to meet the input skew
min 1ns to max 2.6 ns requirement (the
clock trace should be equal length with
data traces in PCB layout).
R/W 0
3 RGMII Internal Delay (ID)
Egress Enable
Enable Egress RGMII-ID Mode
1 = Egress RGMII-ID enabled. An internal
delay is added to egress clock output.
0 = No delay is added, only clock to data
skew applied.
Note: If setting bit [3] = ‘1’, RGMII transmit
clock adds an internal egress delay to
add min 1 ns data to clock skew to
receive side, then the receiving side
may or may not add any internal delay
to meet its own receiving timing require-
ment. (The clock trace should be equal
length with data traces in PCB layout if
no additional external skew on clock is
needed).
R/W 1
TABLE 4-4: PORT REGISTERS (CONTINUED)
Address Name Description Mode Default