Datasheet
KSZ8795CLX
DS00002112B-page 50 2016-2017 Microchip Technology Inc.
4 Flush Static MAC Table Flush the matched entries in static MAC table for
RSTP
1 = Trigger the flush static MAC table operation.
0 = Normal operation.
Note: The matched entry is defined as the
entry in the Forwarding ports field con-
tains a single port and MAC address
with unicast. This port, in turn, has its
learning capability being turned off
(learning disable). Per port, multiple
entries can be qualified as matched
entries.
R/W
(SC)
0
3 Reserved N/A Don’t change RO 1
2 Reserved N/A Don’t change RO 1
1 UNH Mode 1 = The switch will drop packets with 0x8808 in the
T/L filed, or DA = 01-80-C2-00-00-01.
0 = The switch will drop packets qualified as “flow
control” packets.
R/W 0
0 Link Change Age 1 = Link change from “link” to “no link” will cause
fast aging (<800 µs) to age address table faster.
After an age cycle is complete, the age logic will
return to normal (300 ±75 seconds).
Note: If any port is unplugged, all addresses
will be automatically aged out.
R/W 0
Register 3 (0x03): Global Control 1
7 Reserved N/A Don’t change. RO 0
6 2KB Packet Support 1 = Enable 2KB packet support.
0 = Disable 2KB packet support.
R/W 0
5 IEEE 802.3x Transmit
Flow Control Disable
0 = Enables transmit flow control based on AN
result.
1 = Will not enable transmit flow control regardless
of the AN result.
R/W 0
4 IEEE 802.3x Receive
Flow Control Disable
0 = Enables receive flow control based on AN
result.
1 = Will not enable receive flow control regardless
of the AN result.
Note: Bit[5] and Bit[4] default values are con-
trolled by the same pin, but they can be
programmed independently.
R/W 0
3 Frame Length Field
Check
1 = Check frame length field in the IEEE packets. If
the actual length does not match, the packet will be
dropped (for L/T <1500).
R/W 0
2 Aging Enable 1 = Enable aging function in the chip.
0 = Disable aging function.
R/W 1
1 Fast-Age Enable 1 = Turn on fast aging (800 µs). R/W 0
0 Aggressive Back-Off
Enable
1 = Enable more aggressive back-off algorithm in
half duplex mode to enhance performance. This is
not in the IEEE standard.
R/W 0
TABLE 4-3: GLOBAL REGISTERS (CONTINUED)
Address Name Description Mode Default