Datasheet

 2016-2017 Microchip Technology Inc. DS00002112B-page 5
KSZ8795CLX
1.0 INTRODUCTION
1.1 General Description
The KSZ8795CLX is a highly integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce
system cost. It is intended for cost-sensitive applications requiring four 10/100 Mbps copper ports and one 10/100/
1000 Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with
internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program-
mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil-
tering technology, quality-of-service (QoS) priority with four queues, management interfaces, enhanced MIB counters,
high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The
KSZ8795CLX provides support for multiple CPU data interfaces to effectively address both current and emerging fast
Ethernet and Gigabit Ethernet applications where the port 5 GMAC can be configured to any of GMII, RGMII, MII and
RMII modes.
The KSZ8795CLX is built upon industry-leading Ethernet analog and digital technology, with features designed to off-
load host processing and streamline the overall design.
• Four integrated 10/100BASE-T/TX MAC/PHYs
• One integrated 10/100/1000BASE-T/TX GMAC with selectable GMII, RGMII, MII, and RMII interfaces
• Small 80-pin LQFP package
A robust assortment of power-management features including Energy Efficient Ethernet (EEE), PME, and Wake-on-
LAN (WoL) have been designed-in to satisfy energy-efficient environments.
KSZ8795CLX supports two management interface modes of SPI and MIIM only, SPI access all registers, MIIM mode
access all PHYs registers through MDC/MDIO interface.
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM
AUTO MDI/MDIX
AUTO MDI/MDIX
AUTO MDI/MDIX
AUTO MDI/MDIX
SW5-GMII/RGMII/MII/RMII
MDC, MDI/O FOR MIIM
CONTROL REG SPI I/F
LED0 [4:1]
LED1 [4:1]
KSZ8795
10/100
T/TX
EEE PHY1
10/100
T/TX
EEE PHY2
10/100
T/TX
EEE PHY3
10/100
T/TX
EEE PHY4
LED I/F
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100/1000
GMAC 5
SPI
CONTROL
REGISTERS
1K LOOK-UP
ENGINE
QUEUE
MANAGEMENT
BUFFER
MANAGEMENT
FRAME
BUFFER
MIB
COUNTERS
FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY