Datasheet

KSZ8795CLX
DS00002112B-page 34  2016-2017 Microchip Technology Inc.
3.6 Advanced Functionality
3.6.1 QOS PRIORITY SUPPORT
The KSZ8795CLX provides quality-of-service (QoS) for applications such as VoIP and video conferencing. The
KSZ8795CLX offers one, two, or four priority queues per port by setting the Port Control 13 Registers Bit[1] and the Port
Control 0 Registers Bit[0], the 1/2/4 queues split as follows:
• [Port Control 9 Registers Bit[1], Control 0 Bit[0]] = 00 Single output queue as default.
• [Port Control 9 Registers Bit[1], Control 0 Bit[0]] = 01 Egress port can be split into two priority transmit queues.
• [Port Control 9 Registers Bit[1], Control 0 Bit[0]] = 10 Egress port can be split into four priority transmit queues.
The four priority transmit queue is a new feature in the KSZ8795CLX. Queue 3 is the highest priority queue and queue
0 is the lowest priority queue. The Port Control 9 Registers Bit[1] and the Port Control 0 Registers Bit[0] are used to
enable split transmit queues for Ports 1, 2, 3, 4 and 5, respectively. If a Port's transmit queue is not split, high priority
and low priority packets have equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or to use programmable weighted fair
queuing for the four priority queue scale by the Port Control 14, 15, 16 and 17 Registers (default values are 8, 4, 2, 1
by their bits [6:0]).
Register 130 Bit[7:6] Prio_2Q[1:0] is used when the 2-Queue configuration is selected. These bits are used to map the
2-bit result of IEEE 802.1p from the Registers 128, 129 or TOS/DiffServ mapping from Registers 144-159 (for 4 Queues)
into 2-Queue mode with priority high or low.
Please see the descriptions of Register 130 bits [7:6] for detail.
3.6.1.1 Port-Based Priority
With port-based priority, each ingress port is individually classified as a priority 0-3 receiving port. All packets received
at the priority 3 receiving port are marked as high-priority and are sent to the high-priority transmit queue if the corre-
sponding transmit queue is split. The Port Control 0 Registers bits [4:3] is used to enable port-based priority for ports 1,
2, 3, 4 and 5, respectively.
TABLE 3-12: PORT 5 SW5-RMII CONNECTION
SW5-RMII MAC-to-MAC Connection
(PHY Mode)
Description
SW5-RMII MAC-to-PHY Connection
(MAC Mode)
External MAC
KSZ8795CLX
SW5-RMII
Signals
Type External PHY
KSZ8795CLX
SW5-RMII
Signals
Type
REF_CLKI RXC5
Output 50 MHz
in Clock Mode
Reference
Clock
50 MHz REFCLKI5
Input 50 MHz
in Normal
Mode
CRS_DV
RXDV5/
CRSDV5
Output
Carrier Sense/
Receive Data
Valid
CRS_DV TXEN5 Input
— — — Receive Error RXER TXER5 Input
RXD[1:0] RXD5[1:0] Output
Receive Data
Bit[1:0]
RXD[1:0] TXD5[1:0] Input
TX_EN TXEN5 Input
Transmit Data
Enable
TX_EN
RXDV5/
CRSDV5
Output
TXD[1:0] TXD5[1:0] Input
Transmit Data
Bit[1:0]
TXD[1:0] RXD[1:0] Output
50 MHz REFCLKI5
Input 50 MHz
in Normal
Mode
Reference
Clock
REF_CLKI RXC5
Output 50 MHz
in Clock Mode