Datasheet

KSZ8795CLX
DS00002112B-page 32  2016-2017 Microchip Technology Inc.
The Port 5 GMAC5 SW5-GMII interface operates at up to 1000 Mbps. In 1Gbps mode, GMII supports the full-duplex
only. The GMII interface is 8-bits data in each direction. Additional signals on the transmit side indicate when data is
valid or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data
is valid and without physical layer errors. For half-duplex operation in 10/100 Mbps mode, there is a COL signal that
indicates a collision has occurred during transmission.
3.5.2.6 Port 5 GMAC5 SW5-RGMII Interface
Table 3-10 shows the RGMII reduced connections when connecting to an external GMAC or GPHY.
The RGMII interface operates at up to a 1000 Mbps speed rate. Additional transmit and receive signals control the dif-
ferent direction of the data transfer. This RGMII interface supports RGMII Rev 2.0 with adjustable ingress clock and
egress clock delay by the Register 86 (0x56).
For RGMII to correctly configure with the connection partner, Register 86 (0x56) bits [4:3] need to be set up correctly. A
configuration table is found in Table 3-11.
MCOL COL5 Output Collision
Detection
MCOL COL5 Input
MCRS CRS5 Output Carrier Sense MCRS CRS5 Input
MRXDV RXDV5 Output Receive Data
Valid
MRXDV TXEN5 Input
MRXER RXER5 Output Receive Error MRXER TXER5 Input
MRXD[7:0] RXD5[7:0] Output Receive Data
Bits[7:0]
MRXD[7:0] TXD5[7:0] Input
MGRXC GRXC5 Output Receive Clock MGRXC GTXC5 Input
TABLE 3-10: PORT 5 SW5-RGMII CONNECTION
KSZ8795CLX SW5-RGMII Connection
Description
External GMAC/GPHY
KSZ8795CLX SW5-RGMII
Signals
Type
MRX_CTL TXD5_CTL Input Transmit Control
MRXD[3:0] TXD5[3:0] Input Transmit Data Bit[3:0]
MRX_CLK GTX5_CLK Input Transmit Clock
MTX_CLK RXD5_CTL Output Receive Control
MTXD[3:0] RXD5[3:0] Output Receive Data Bit[3:0]
MGTX_CLK GRXC5 Output Receive Clock
TABLE 3-11: PORT 5 SW5-RGMII CLOCK DELAY CONFIGURATION WITH CONNECTION
PARTNER
KSZ8795CLX
Register 86 Bits[4:3]
Configuration
RGMII Clock Mode
(Receive and
Transmit)
KSZ8795CLX
Register 86 (0x56)
KSZ8795CLX RGMII
Clock Delay/Slew
Configuration
Connection Partner
RGMII Clock
Configuration
(Note 3-1)
Bit[4:3] = 11 Mode Ingress Clock Input Bit[4] = 1 Delay No Delay
Egress Clock Output Bit[3] = 1 Delay No Delay
Bit[4:3] = 10 Mode Ingress Clock Input Bit[4] = 1 Delay No Delay
Egress Clock Output Bit[3] = 1 No Delay Delay
TABLE 3-9: PORT 5 SW5-GMII CONNECTION (CONTINUED)
GMAC-to-GMAC Connection
KSZ8795CLX SW5-GMII GPHY Mode
Description
GMAC-to-GPHY Connection
KSZ8795CLX SW5-GMII GMAC Mode
External
GMAC
KSZ8795CLX
SW5-GMII
Signals
Type
External
GPHY
KSZ8795CLX
SW5-GMII
Signals
Type