Datasheet

 2016-2017 Microchip Technology Inc. DS00002112B-page 31
KSZ8795CLX
The MII interface operates in either MAC mode or PHY mode. These interfaces are nibble-wide data interfaces, so they
run at one-quarter the network bit rate (not encoded). Additional signals on the transmit side indicate when data is valid
or when an error occurs during transmission. Likewise, the receive side has indicators that convey when the data is valid
and without physical layer errors. For half-duplex operation, there is a COL signal that indicates a collision has occurred
during transmission.
Note: Normally MRXER would indicate a receive error coming from the physical layer device. MTXER would indi-
cate a transmit error from the MAC device. These signals are not appropriate for this configuration. For PHY
mode operation with an external MAC, if the device interfacing with the KSZ8795CLX has an MRXER pin,
it can be tied low. For MAC mode operation with an external PHY, if the device interfacing with the KSZ8795-
CLX has an MTXER pin, it can be tied low.
3.5.2.5 Port 5 GMAC5 SW5-GMII Interface
Table 3-9 shows two GMII connection methods when connected to an external GMAC or GPHY.
• The first is an external GMAC connecting in SW5-GMII GPHY mode.
• The second is an external GPHY connecting in SW5-GMII GMAC mode.
The GMAC mode or GPHY mode setting is determined by the strap Pin 62 LED2_1.
TABLE 3-8: PORT 5 SW5-MII CONNECTION
MAC-to-MAC Connection
KSZ8795CLX SW5-MII PHY Mode
Description
MAC-to-PHY Connection
KSZ8795CLX SW5-MII MAC Mode
External MAC
KSZ8795CLX
SW5-MII
Signals
Type External PHY
KSZ8795CLX
SW5-MII
Signals
Type
MTXEN TXEN5 Input Transmit
Enable
MTXEN RXDV5 Output
MTXER TXER5 Input Transmit Error MTXER RXER5 Output
MTXD[3:0] TXD5[3:0] Input Transmit Data
Bit[3:0]
MTXD[3:0] RXD5[3:0] Output
MTXC TXC5 Output Transmit Clock MTXC RXC5 Input
MCOL COL5 Output Collision
Detection
MCOL COL5 Input
MCRS CRS5 Output Carrier Sense MCRS CRS5 Input
MRXDV RXDV5 Output Receive Data
Valid
MRXDV TXEN5 Input
MRXER RXER5 Output Receive Error MRXER TXER5 Input
MRXD[3:0] RXD5[3:0] Output Receive Data
Bit[3:0]
MRXD[3:0] TXD5[3:0] Input
MRXC RXC5 Output Receive Clock MRXC TXC5 Input
TABLE 3-9: PORT 5 SW5-GMII CONNECTION
GMAC-to-GMAC Connection
KSZ8795CLX SW5-GMII GPHY Mode
Description
GMAC-to-GPHY Connection
KSZ8795CLX SW5-GMII GMAC Mode
External
GMAC
KSZ8795CLX
SW5-GMII
Signals
Type
External
GPHY
KSZ8795CLX
SW5-GMII
Signals
Type
MTXEN TXEN5 Input Transmit
Enable
MTXEN RXDV5 Output
MTXER TXER5 Input Transmit Error MTXER RXER5 Output
MTXD[7:0] TXD5[7:0] Input Transmit Data
Bits[7:0]
MTXD[7:0] RXD5[7:0] Output
MGTXC GTXC5 Input Transmit Clock MGTXC GRXC5 Output