Datasheet

KSZ8795CLX
DS00002112B-page 30  2016-2017 Microchip Technology Inc.
3.5.2.1 Standard GMII/MII Interface
For MII and GMII, the interface is capable of supporting 10/100 Mbps and 1000 Mbps operation. Data and delimiters
are synchronous to clock references. It provides independent four-/eight-bit-wide transmit and receive data paths and
uses signal levels, two media status signals are provided. The CRS indicates the presence of carrier, and the COL indi-
cates the occurrence of a collision. Both half- and full-duplex operations are provided by MII and full-duplex operation
is used for GMII.
The GMII is based on the MII. MII signal names have been retained and the functions of most signals are the same, but
additional valid combinations of signals have been defined for 1000 Mbps operation. The GMII supports only 1000 Mbps
operation. Operation at 10 Mbps and 100 Mbps is supported by the MII interface.
The MII transfers data using 4-bit words (nibble) in each direction. It is clocked at 2.5/25 MHz to achieve 10/100 Mbps
speed. The GMII transfers data using 8-bit words (nibble) in each direction, clocked at 125 MHz to achieve 1000 Mbps
speed.
3.5.2.2 Reduced Gigabit Media Independent Interface (RGMII)
RGMII is intended to be an alternative to the IEEE802.3u MII and the IEEE802.3z GMII. The principle objective is to
reduce the number of pins required to interconnect the GMAC and the GPHY in a cost effective and technology inde-
pendent manner. In order to accomplish this objective, the data paths and all associated control signals will be reduced
and control signals will be multiplexed together and both edges of the clock will be used. For Gigabit operation, the
clocks will operate at 125 MHz with the rising edge and falling edge to latch the data.
3.5.2.3 Reduced Media Independent Interface (RMII)
The reduced media independent interface (RMII) specifies a low pin count media independent interface (MII). The
KSZ8795CLX supports the RMII interface on the Port 5 GMAC5 and provides the following key characteristics:
• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz clock reference (provided internally or externally): in internal mode, the chip provides a ref-
erence clock from the RXC5 to the opposite clock input pin for RMII interface. In external mode, the chip receives
50 MHz reference clock from an external oscillator or opposite RMII interface.
• Provides independent 2-bit wide (bi-bit) transmit and receive data paths.
3.5.2.4 Port 5 GMAC5 SW5-MII Interface
Table 3-8 shows two connection methods.
1. The first is an external MAC connecting in SW5-MII PHY mode.
2. The second is an external PHY connecting in SW5-MII MAC mode.
The MAC mode or PHY mode setting is determined by the strap pin 62 LED2_1.
TABLE 3-7: SIGNALS OF GMII/RGMII/MII/RMII
Direction Type GMII RGMII MII RMII
Input (Output) GTXC GTXC TXC REFCLKI
Input TXER — TXER —
Input TXEN TXD_CTL TXEN TXEN
Input (Output) COL — COL —
Input TXD[7:0] TXD[3:0] TXD[3:0] TXD[1:0]
Input (Output) GRXC GRXC RXC RXC
Output RXER — RXER RXER
Output RXDV RXD_CTL RXDV CRS_DV
Input (Output) CRS — CRS —
Output RXD[7:0] RXD[3:0] RXD[3:0] RXD[1:0]