Datasheet

KSZ8795CLX
DS00002112B-page 22  2016-2017 Microchip Technology Inc.
The KSZ8795CLX supports enhanced power management in a low power state, with energy detection to ensure low
power dissipation during device idle periods. There are multiple operation modes under the power management function
which are controlled by the Register 14 Bits[4:3] and the Port Control 10 Register Bit[3] as:
• Register 14 Bits[4:3] = 00 Normal Operation Mode
• Register 14 Bits[4:3] = 01 Energy Detect Mode
• Register 14 Bits[4:3] = 10 Soft Power-Down Mode
• Register 14 Bits[4:3] = 11 Reserved
The Port Control 10 Register 29, 45, 61, 77 Bit[3] = 1 are for the port-based power-down mode. Table 3-3 indicates all
internal function blocks’ status under four different power management operation modes.
3.4.1 NORMAL OPERATION MODE
This is the default setting Bits[4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8795CLX is in
normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is ready for CPU read
or writes.
During normal operation mode, the host CPU can set the Bits [4:3] in Register 14 to change the current normal operation
mode to any one of the other three power management operation modes.
3.4.2 ENERGY DETECT MODE
Energy detect mode provides a mechanism to save more power than in the normal operation mode when the KSZ8795-
CLX port is not connected to an active link partner. In this mode, the device will save more power when the cables are
unplugged. If the cable is not plugged in, the device can automatically enter a low power state: the energy detect mode.
In this mode, the device will keep transmitting 120 ns width pulses at a rate of 1 pulse per second. Once activity resumes
due to plugging a cable in or attempting by the far end to establish link, the device can automatically power up to normal
power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low-power state. While in low power state, the
device reduces power consumption by disabling all circuitry except the energy-detect circuitry of the receiver. The
energy detect mode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8795CLX is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bits [7:0]
Go-Sleep time in Register 15, KSZ8795CLX will go into low power state. When KSZ8795CLX is in low power state, it
will keep monitoring the cable energy. Once the energy is detected from the cable, the device will enter normal power
state. When the device is at normal power state, it is able to transmit or receive packet from the cable.
3.4.3 SOFT POWER-DOWN MODE
The soft power-down mode is entered by setting bits [4:3] = 10 in Register 14. When KSZ8795CLX is in this mode, all
PLL clocks are disabled, also all of PHYs and the MACs are off. Any dummy host access will wake-up this device from
current soft power down mode to normal operation mode and internal reset will be issued to make all internal registers
go to the default values.
VDD12A 1 1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to
power the internal analog and digital cores.
VDD12D 26, 42, 73
GNDA 3, 21, 78 Analog ground.
GNDD 27, 33, 47, 61, 71 Digital ground.
TABLE 3-3: INTERNAL FUNCTION BLOCK STATUS
KSZ8795CLX Function
Blocks
Power Management Operation Modes
Normal Mode Energy Detect Mode Soft Power-Down Mode
Internal PLL Clock Enabled Disabled Disabled
TX/RX PHY Enabled Energy Detect at RX Disabled
MAC Enabled Disabled Disabled
Host Interface Enabled Disabled Disabled
TABLE 3-2: KSZ8795CLX VOLTAGE OPTIONS AND REQUIREMENTS (CONTINUED)
Power Signal
Name
Device Pin Requirement