Datasheet

KSZ8795CLX
DS00002112B-page 14  2016-2017 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
The KSZ8795CLX contains four 10/100 physical layer transceivers, four media access control (MAC) units, and one
Gigabit media access control (GMAC) unit with an integrated Layer 2-managed switch. The device runs in two modes.
The first mode is as a four-port standalone switch and the second is as a five-port switch with fifth port that is provided
through a Gigabit media independent interface that supports GMII, RGMII, MII, and RMII. This is useful for implementing
an integrated broadband router.
The KSZ8795CLX has the flexibility to reside in a managed mode. In a managed mode, a host processor has complete
control of the KSZ8795CLX via the SPI bus, or the MDC/MDIO interface.
On the media side, the KSZ8795CLX supports IEEE 802.3 10BASE-T, 100BASE-TX on all copper ports with Auto- MDI/
MDI-X. The KSZ8795CLX can be used as a fully-managed five-port switch or hooked up to a microprocessor via its SW-
GMII/RGMII/MII/RMII interfaces to allow for integrating into a variety of environments.
Physical signal transmission and reception are enhanced through the use of patented analog circuitry and DSP tech-
nology that makes the design more efficient and allows for reduced power consumption and smaller die size.
Major enhancements from the KSZ8995 and KS8895 to the KSZ8795CLX include more host interface options such as
the GMII and RGMII interfaces, power-saving features such as IEEE 802.1az Energy Efficient Ethernet (EEE), MLD
snooping, Wake-on-LAN (WoL), port-based ACL filtering for the port security, enhanced quality-of-service (QoS) priority,
rapid spanning tree, IGMP snooping, port mirroring support, and flexible rate limiting.
3.1 Physical Layer (PHY)
3.1.1 100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-
version, and MLT3 encoding and transmission. The circuit starts with a parallel-to-serial conversion, which converts the
MII data from the MAC into a 125 MHz serial bit stream. The data and control stream is then converted into 4B/5B coding
followed by a scrambler. The serialized data is further converted from NRZ-to-NRZI format, and then transmitted in
MLT3 current output. The output current is set by an external 1% 12.4 k resistor for the 1:1 transformer ratio. It has a
typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude balance, overshoot, and
timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
3.1.2 100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, descrambling, 4B/5B decoding, and serial-to-parallel conversion. The receiv-
ing side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair cable.
Since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its char-
acteristics to optimize the performance. In this design, the variable equalizer will make an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and can self-adjust against environmental changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. The signal is then sent through the descrambler followed by the
4B/5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.1.3 PLL CLOCK SYNTHESIZER
The KSZ8795CLX generates 125 MHz, 83 MHz, 41 MHz, 25 MHz, and 10 MHz clocks for system timing. Internal clocks
are generated from an external 25 MHz crystal or oscillator.
3.1.4 SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
The data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). This can generate a 2047-
bit non-repetitive sequence. The receiver will then descramble the incoming data stream with the same sequence at the
transmitter.