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KSZ8795CLX

DS00002112B-page 12  2016-2017 Microchip Technology Inc.

The KSZ8795CLX can function as a managed switch and utilizes strap-in pins to configure the device for different

modes. The strap-in pins are configured by using external pull-up/down resistors to create a high or low state on the

pins which are sampled during the power-down reset or warm reset. The functions are described in following table.

TABLE 2-2: STRAP-IN OPTIONS - KSZ8795CLX

Pin Number Pin Name

Type

(Note 2-2)

Description

24, 25 LED3[1,0] Ipu/O

Switch Port 5 GMAC5 Interface Mode Select:

Strap Option:

00 = MII for SW5-MII

01 = RMII for SW5-RMII

10 = GMII for SW5-GMII

11 = RGMII for SW5-RGMII (Default)

62 LED2_1 Ipu/O

Port 5 GMII/MII and RMII Mode Select:

Strap Option:

When Port 5 is GMII/MII mode:

PU = GMII/MII is in GMAC/MAC mode. (Default)

PD = GMII/MII is in GPHY/PHY mode.

Note: When set GMAC5 GMII to GPHY mode, the CRS and

COL pins will change from the input to output. When set

MII to PHY mode, the CRS, COL, RXC and TXC pins will

change from the input to output.

When Port 5 is RMII mode:

PU = Clock mode in RMII, using 25 MHz OSC clock and provide

50 MHz RMII clock from pin RXC5.

PD = Normal mode in RMII, the TXC5/REFCLKI5 pin on the Port 5

RMII will receive an external 50 MHz clock

Note: Port 5 also can use either an internal or external clock in

RMII mode based on this strap pin or the setting of the

63 LED2_0 Ipu/O REFCLKO Enable:

Strap Option:

PU = REFCLK_O (25 MHz) is enabled. (Default)

PD = REFCLK_O is disabled.

64 LED1_1 Ipu/O PLL Clock Source Select:

Strap Option:

PU = Still use 25 MHz clock from XI/XO pin even though it is in Port

5 RMII normal mode.

PD = Use external clock from TXC5 pin in Port 5 RMII normal mode.

Note: If received clock in Port 5 RMII normal mode with bigger

clock jitter, still can select to use the 25 MHz crystal/oscil-

lator as switch’s clock source.

65 LED1_0 Ipu/O Port 5 Gigabit Select:

Strap Option:

PU = 1 Gbps in GMII/RGMII mode (Default)

PD = 10/100 Mbps in GMII/RGMII mode.

Note: Programmable through internal register also