Datasheet

KSZ8795CLX
DS00002112B-page 108  2016-2017 Microchip Technology Inc.
Please note that all per-port MIB counters are Read-Clear.
KSZ8795CLX also offers the statistic control capability by the Global Register 8 to control MIB to flush counter or freeze
counter per port.
The KSZ8795CLX provides a total of 36 MIB counters per port. These counters are used to monitor the port activity for
network management and maintenance. These MIB counters are read using indirect memory access, per the following
examples.
1. MIB counter read (read Port 1 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counters selected)
Write to Register 111 with 0xd (trigger the read operation)
Then:
Read Register 116 (counter value [39:32])
// If Bit [38] = 1, there was a counter overflow
Read Register 117 (counter value [31:24])
Read Register 118 (counter value [23:16])
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])
2. MIB counter read (read Port 2 Rx64Octets counter)
Write to Register 110 with 0x1c (read MIB counter selected)
Write to Register 111 with 0x2d (trigger the read operation)
Then:
Read Register 116 (counter value [39:32])
// If Bit[38] = 1, there was a counter overflow
Read Register 117 (counter value [31:24])
Read Register 118 (counter value [23:16])
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])
3. MIB counter read (read Port 1 TX drop packets)
Write to Register 110 with 0x1d
Write to Register 111 with 0x03
Then:
Read Register 116 (counter value [39:32])
// If Bit[38] = 1, there was a counter overflow
Read Register 119 (counter value [15:8])
Read Register 120 (counter value [7:0])
TABLE 4-30: FORMAT OF ALL DROPPED PACKET MIB COUNTER (IN TABLE 4-28)
Address Name Description Mode Default
38 Overflow 1 = Counter overflow.
0 = No Counter overflow.
RO 0
37 Count Valid 1 = Counter value is valid.
0 = Counter value is not valid.
RO 0
36 - 16 Reserved — RO All ‘0’
15 - 0 Counter
Values
Counter value RO 0