Datasheet

 2016-2017 Microchip Technology Inc. DS00002112B-page 105
KSZ8795CLX
Programming Examples:
Read Operation
1. Use the Indirect Access Control Register to select register to be read, to read the EEE Global Register 0 (Global
EEE QM Buffer Control Register).
2. Write 0x30 to the Register 110 (0x6E) // EEE selected and read operation, and 4 MSBs of port number = 0 for
the global register.
3. Write 0x30 to the Indirect Register 111 (0x6F) // trigger the read operation and ready to read the EEE Global Reg-
ister 0 Bits[15:8].
4. Read the Indirect Byte Register 160 (0xA0) // Get the Bits[15:8] value of the EEE Global Register 0.
Write Operation
1. Write 0x20 to Register 110 (0x6E) // EEE selected and write operation, 4 MSBs of port number = 0 is for global
register.
2. Write 0x31 to Register 111 (0x6F) // select the offset address, ready to write the EEE Global Register 0 Bits[7:0].
3. Write new value to the Indirect Byte Register 160 (0xA0) Bits[7:0].
4.10 Management Information Base (MIB) Counters
The MIB counters are provided on per port basis. These counters are read using indirect memory access as in Ta b l e 4-
26.
EEE Port Register 6
Port EEE LPI Recovery Time Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2E (Bits[15:8]), 0x2F (Bits[7:0])
Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
15 - 8 Reserved — RO 1
7 - 0 LPI Recovery
Counter
This register specifies the time that the MAC device
has to wait before it can start to send out packets.
This value should be the maximum of the LPI
recovery time between local device and remote
device. The unit is 640 ns.
The default is about 25 µs = 39 (0x27) × 640 ns
Note: This value can be adjusted if PHY
recovery time is less than the standard
20.5 µs for the packets to be sent out
quickly from EEE LPI mode.
R/W 0x27
TABLE 4-26: PORT MIB COUNTER INDIRECT MEMORY OFFSETS
Offset Counter Name Description
0x0 RxHiPriorityByte Rx hi-priority octet count including bad packets.
0x1 RxUndersizePkt Rx undersize packets w/good CRC.
0x2 RxFragments Rx fragment packets w/bad CRC, symbol errors or alignment errors.
0x3 RxOversize Rx oversize packets w/good CRC (maximum: 1536 or 1522 bytes).
0x4 RxJabbers Rx packets longer than 1522 bytes w/either CRC errors, alignment
errors, or symbol errors (depends on max packet size setting) or Rx
packets longer than 1916 bytes only.
0x5 RxSymbolError Rx packets w/ invalid data symbol and legal preamble, packet size.
0x6 RxCRCerror Rx packets within (64,1522) bytes w/an integral number of bytes and a
bad CRC (upper limit depends on max packet size setting).
TABLE 4-25: EEE PORT REGISTERS (CONTINUED)
Address Name Description Mode Default