Datasheet

KSZ8795CLX
DS00002112B-page 104  2016-2017 Microchip Technology Inc.
EEE Port Register 5
Port EEE Control Register
Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register,
Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
Offset: 0x2C (Bits[15:8]), 0x2D (bits[7:0])
Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
15 10BT EEE
Disable
1 = 10BT EEE mode is disabled
0 = 10BT EEE mode is enabled
Note: 10BT EEE mode save power by reduc-
ing signal amplitude only.
R/W 1
14 - 8 Reserved — RO 7h’0
7 H/W Based
EEE NP
Auto-Negoti-
ation Enable
1 = H/W will automatically perform EEE capability
exchange with Link Partner through next page
exchange. EEE 100BT enable (Bit[0] of this regis-
ter). Will be set by H/W if EEE capability is
matched.
0 = H/W-based EEE capability exchange is off.
EEE capability exchange is done by software.
R/W 1
6 H/W 100BT
EEE Enable
Status
1 = 100BT EEE is enabled by H/W-based np
exchange
0 = 100BT EEE is disabled
R0
5TX LPI
Received
1 = Indicates that the transmit PCS has received
low power idle signaling one or more times since
the register was last read.
0 = Indicates that the PCS has not received low
power idle signaling.
This bit is cleared after reading.
R/RC 0
4TX LPI
Indication
1 = Indicates that the transmit PCS is currently
receiving low power idle signals.
0 = Indicates that the PCS is not currently receiving
low power idle signals.
R0
3RX LPI
Received
1 = Indicates that the receive PCS has received
low power idle signaling one or more times since
the register was last read.
0 = Indicates that the PCS has not received low
power idle signaling.
This bit is cleared after reading.
R/RC 0
2RX LPI
Indication
1 = Indicates that the receive PCS is currently
receiving low power idle signals.
0 = Indicates that the PCS is not currently receiving
low power idle signals.
R0
1 EEE SW
Mode Enable
1 = EEE is enabled through S/W setting Bit[0] of
this register.
0 = EEE is enabled through H/W Auto-Negotiation
R/W 0
0 EEE SW
100BT
Enable
1 = EEE 100BT is enabled
0 = EEE 100BT is disabled
Note: This bit could be set by S/W or H/W if H/
W-based EEE Next Page Auto-Negotia-
tion enable is on.
R/W 0
TABLE 4-25: EEE PORT REGISTERS (CONTINUED)
Address Name Description Mode Default