KSZ8795CLX Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces - Target Applications • Industrial Ethernet Applications that Employ IEEE 802.3-Compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP, etc.
KSZ8795CLX - IGMP v1/v2/v3 Snooping for Multicast Packet Filtering - QoS/CoS Packets Prioritization Support: 802.1p, DiffServ-Based and Re-Mapping of 802.
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KSZ8795CLX Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 5 2.0 Pin Description and Configuration ................................................................................................................................................... 6 3.0 Functional Description ...................................................................
KSZ8795CLX 1.0 INTRODUCTION 1.1 General Description The KSZ8795CLX is a highly integrated, Layer 2-managed, 5-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring four 10/100 Mbps copper ports and one 10/100/ 1000 Mbps Gigabit uplink port. The KSZ8795CLX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination.
KSZ8795CLX 2.
KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX Pin Number Pin Name Type Note 2-1 Port 1 VDD12A P — 1.2V Core Power 2 VDDAT P — 3.3V or 2.5V Analog Power. 3 GNDA GND — Analog Ground. 4 RXP1 I 1 Port 1 Physical Receive Signal + (Differential). 5 RXM1 I 1 Port 1 Physical Receive Signal - (Differential). 6 TXP1 O 1 Port 1 Physical Transmit Signal + (Differential). 7 TXM1 O 1 Port 1 Physical Transmit Signal - (Differential).
KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED) Pin Number Pin Name Type Note 2-1 Port 26 VDD12D P — 1.2V Core Power. 27 GNDD GND — Digital Ground. 28 LED4_1 Ipu/O 4 Port 4 LED Indicator 1: See Global Register 11 bits [5:4] for details. 29 TXEN5/ TXD5_CTL Ipd 5 GMII/MII/RMII: Port 5 Switch transmit enable. RGMII: Transmit data control. 30 TXD5_0 Ipd 5 GMII/RGMII/MII/RMII: Port 5 switch transmit Bit[0].
KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED) Pin Number Pin Name Type Note 2-1 Port 45 RXD5_0 Ipd/O 5 GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[0]. 46 RXD5_1 Ipd/O 5 GMII/RGMII/MII/RMII: Port 5 Switch receive Bit[1]. 47 GNDD GND — Digital Ground. 48 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. 49 RXD5_2 Ipd/O 5 GMII/RGMII/MII: Port 5 Switch receive Bit[2].
KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED) Pin Number Pin Name Type Note 2-1 Port 62 LED2_1 Ipu/O 2 Description Port 2 LED Indicator 1: See Global Register 11 bits [5:4] for details. Strap Option: Port 5 GMII/MII and RMII mode select When Port 5 is GMII/MII mode: PU = GMII/MII is in GMAC/MAC mode. (Default) PD = GMII/MII is in GPHY/PHY mode. Note: When set GMAC5 GMII to GPHY mode, the CRS and COL pins will change from the input to output.
KSZ8795CLX TABLE 2-1: SIGNALS - KSZ8795CLX (CONTINUED) Pin Number Pin Name Type Note 2-1 Port 67 SCL_MDC Ipu All Clock Input for SPI or MDC/MDIO Interface: Input clock up to 50 MHz in SPI slave mode. Input clock up to 25 MHz in MDC/MDIO for MIIM access. 68 SDA_MDIO Ipu/O All Data for SPI or MDC/MDIO Interface: Serial data input in SPI slave mode. MDC/MDIO interface data input/output. 69 SPIS_N Ipu All SPI Slave Mode Chip Select (Active-Low): SPI data transfer start in SPI slave mode.
KSZ8795CLX The KSZ8795CLX can function as a managed switch and utilizes strap-in pins to configure the device for different modes. The strap-in pins are configured by using external pull-up/down resistors to create a high or low state on the pins which are sampled during the power-down reset or warm reset. The functions are described in following table.
KSZ8795CLX TABLE 2-2: STRAP-IN OPTIONS - KSZ8795CLX (CONTINUED) Pin Number Pin Name Type (Note 2-2) 66 SPIQ Ipd/O Description Serial Bus Configuration Strap Option: PD = SPI slave mode. (Default) PU = MDC/MDIO mode. Note: Note 2-2 An external pull-up or pull-down resistor is requested. If the uplink port is used for the RGMII interface, SPI mode is recommend for setting register 86 (0x56) bits [4:3] for RGMII v2.0; MDC/MDIO mode can’t set this feature.
KSZ8795CLX 3.0 FUNCTIONAL DESCRIPTION The KSZ8795CLX contains four 10/100 physical layer transceivers, four media access control (MAC) units, and one Gigabit media access control (GMAC) unit with an integrated Layer 2-managed switch. The device runs in two modes. The first mode is as a four-port standalone switch and the second is as a five-port switch with fifth port that is provided through a Gigabit media independent interface that supports GMII, RGMII, MII, and RMII.
KSZ8795CLX 3.1.5 10BASE-T TRANSMIT The 10BASE-T output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents are at least 27 dB below the fundamental when driven by an all-ones Manchester-encoded signal. 3.1.6 10BASE-T RECEIVE On the receive side, input buffers and level detecting squelch circuits are employed.
KSZ8795CLX 3.1.7.2 Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. The following diagram shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
KSZ8795CLX FIGURE 3-3: 3.1.9 AUTO-NEGOTIATION AND PARALLEL OPERATION LINKMD® CABLE DIAGNOSTICS The LinkMD feature utilizes time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes the shape of the reflected signal.
KSZ8795CLX 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) The ‘11’ case, invalid test, occurs when the KSZ8795CLX is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8795CLX to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5.
KSZ8795CLX 3.1.10 ON-CHIP TERMINATION AND INTERNAL BIASING The KSZ8795CLX reduces the board cost and simplifies the board layout by using on-chip termination resistors for all ports and RX/TX differential pairs without the external termination resistors.
KSZ8795CLX skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. To ensure no packet loss in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following: • Aggressive backoff (Register 3, Bit[0]) • No excessive collision drop (Register 4, Bit[3]) • Back pressure (Register 4, Bit[5]) These bits are not set as the default because this is not the IEEE standard. 3.2.
KSZ8795CLX The KSZ8795CLX will not forward the following packets: • Error packets. These include framing errors, frame check sequence (FCS) errors, alignment errors, and illegal size packet errors. • IEEE802.3x PAUSE frames. KSZ8795CLX intercepts these packets and performs full duplex flow control accordingly. • "Local" packets. Based on destination address (DA) lookup, if the destination port from the lookup table matches the port from which the packet originated, the packet is defined as "local.
KSZ8795CLX TABLE 3-2: KSZ8795CLX VOLTAGE OPTIONS AND REQUIREMENTS (CONTINUED) Power Signal Name Device Pin VDD12A 1 VDD12D 26, 42, 73 Requirement 1.2V core power. Filtered 1.2V input voltage. These pins feed 1.2V to power the internal analog and digital cores. GNDA 3, 21, 78 Analog ground. GNDD 27, 33, 47, 61, 71 Digital ground. The KSZ8795CLX supports enhanced power management in a low power state, with energy detection to ensure low power dissipation during device idle periods.
KSZ8795CLX 3.4.4 PORT-BASED POWER-DOWN MODE In addition, the KSZ8795CLX features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via the Port Control 10 Register Bit[3], or MIIM PHY Register 0 Bit[11]. 3.4.
KSZ8795CLX 3.4.5.1 LPI Signaling LPI signaling allows switch to indicate to the PHY, and to the link partner, that a break in the data stream is expected, and switch can use this information to enter power-saving modes that require additional time to resume normal operation. LPI signaling also informs the switch when the link partner has sent such an indication. The definition of LPI signaling uses of the MAC for simplified full duplex operation (with carrier sense deferral).
KSZ8795CLX FIGURE 3-6: TRAFFIC ACTIVITY AND EEE LPI OPERATIONS LOW POWER ACTIVE DATA/ IDLE IDLE Tr QUIET WAKE Tq QUIET REFRESH REFRESH SLEEP DATA/ IDLE Ts QUIET ACTIVE Tw_PHY Tw_SYSTEM Ts = THE PERIOD OF TIME THAT THE PHY TRANSMITS THE SLEEP SIGNAL BEFORE TURNING ALL TRANSMITTERS OFF, 200 ≤ Ts ≤ 220 USED IN 100BASE-TX. Tq = THE PERIOD OF TIME THAT THE PHY REMAINS QUIET BEFORE SENDING THE REFRESH SIGNAL, 20_000 ≤ Tq ≤ 22_000 USED IN 100BASE-TX.
KSZ8795CLX There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in their own ways. 3.4.6.1 Direction of Energy The energy is detected from the cable and is continuously presented for a time longer than pre-configured value, especially when this energy change may impact the level at which the system should re-enter to the normal power state. 3.4.6.
KSZ8795CLX 3.5 Interfaces The KSZ8795CLX device incorporates a number of interfaces to enable it to be designed into a standard network environment as well as a vendor unique environment. The available interfaces are summarized in Table 3-4. The detail of each usage in this table is provided in the sections that follow.
KSZ8795CLX FIGURE 3-7: SPI ACCESS TIMING S_CS S_CS S_CLK S_CLK S_DI S_DI 0 1 0 A11 A10 A9 A7 A8 A6 A5 A4 A3 A2 A1 A0 TR D7 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 S_DO S_DO Write WRITE Command COMMAND WRITE Write Data DATA WRITE Write Address ADDRESS A) SPI Write Cycle A) SPI WRITE CYCLE S_CS S_CS S_CLK S_CLK S_DI S_DI S_DO S_DO 0 1 1 A11 A10 A9 A7 A8 A6 A5 A4 A3 A2 A1 A0 TR D7 Read READ Command COMMAND D6 D5 D4 D3 READ Read Data DATA ReadREAD Address ADDRESS B)
KSZ8795CLX 3.5.1.2 MII Management Interface (MIIM) The KSZ8795CLX supports the standard IEEE 802.3 MII management interface, also known as the management data input/output (MDIO) interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8795CLX. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further details on the MIIM interface are found in the IEEE 802.3u Specification.
KSZ8795CLX TABLE 3-7: SIGNALS OF GMII/RGMII/MII/RMII Direction Type GMII RGMII MII RMII Input (Output) GTXC GTXC TXC REFCLKI Input TXER — TXER — Input TXEN TXD_CTL TXEN TXEN Input (Output) COL — COL — Input TXD[7:0] TXD[3:0] TXD[3:0] TXD[1:0] Input (Output) GRXC GRXC RXC RXC Output RXER — RXER RXER Output RXDV RXD_CTL RXDV CRS_DV Input (Output) CRS — CRS — Output RXD[7:0] RXD[3:0] RXD[3:0] RXD[1:0] 3.5.2.
KSZ8795CLX TABLE 3-8: PORT 5 SW5-MII CONNECTION MAC-to-MAC Connection KSZ8795CLX SW5-MII PHY Mode MAC-to-PHY Connection KSZ8795CLX SW5-MII MAC Mode Description External MAC KSZ8795CLX SW5-MII Signals Type External PHY KSZ8795CLX SW5-MII Signals Type MTXEN TXEN5 Input Transmit Enable MTXEN RXDV5 Output MTXER TXER5 Input Transmit Error MTXER RXER5 Output MTXD[3:0] TXD5[3:0] Input Transmit Data Bit[3:0] MTXD[3:0] RXD5[3:0] Output MTXC TXC5 Output Transmit Clock MTXC RXC5 In
KSZ8795CLX TABLE 3-9: PORT 5 SW5-GMII CONNECTION (CONTINUED) GMAC-to-GMAC Connection KSZ8795CLX SW5-GMII GPHY Mode GMAC-to-GPHY Connection KSZ8795CLX SW5-GMII GMAC Mode Description External GMAC KSZ8795CLX SW5-GMII Signals Type MCOL COL5 Output MCRS CRS5 MRXDV RXDV5 External GPHY KSZ8795CLX SW5-GMII Signals Type Collision Detection MCOL COL5 Input Output Carrier Sense MCRS CRS5 Input Output Receive Data Valid MRXDV TXEN5 Input MRXER RXER5 Output Receive Error MRXER TXER5
KSZ8795CLX TABLE 3-11: PORT 5 SW5-RGMII CLOCK DELAY CONFIGURATION WITH CONNECTION PARTNER (CONTINUED) KSZ8795CLX Register 86 Bits[4:3] Configuration Bit[4:3] = 01 Mode Bit[4:3] = 00 Mode Note 3-1 RGMII Clock Mode (Receive and Transmit) KSZ8795CLX Register 86 (0x56) KSZ8795CLX RGMII Clock Delay/Slew Configuration Connection Partner RGMII Clock Configuration (Note 3-1) Ingress Clock Input Bit[4] = 0 (default) No Delay Delay Egress Clock Output Bit[3] = 0 (default) Delay No Delay Ingress Clock I
KSZ8795CLX TABLE 3-12: PORT 5 SW5-RMII CONNECTION SW5-RMII MAC-to-MAC Connection (PHY Mode) SW5-RMII MAC-to-PHY Connection (MAC Mode) Description External MAC KSZ8795CLX SW5-RMII Signals Type External PHY KSZ8795CLX SW5-RMII Signals Type REF_CLKI RXC5 Output 50 MHz in Clock Mode Reference Clock 50 MHz REFCLKI5 Input 50 MHz in Normal Mode CRS_DV RXDV5/ CRSDV5 Output Carrier Sense/ Receive Data Valid CRS_DV TXEN5 Input — — — Receive Error RXER TXER5 Input RXD[1:0] RXD5[1:0] Ou
KSZ8795CLX 3.6.1.2 802.1p-Based Priority For 802.1p-based priority, the KSZ8795CLX examines the ingress (incoming) packets to determine whether they are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping” value, as specified by the Registers 128 and 129, both Register 128 and 129 can map 3-bit priority field of 0-7 value to 2-bit result of 0-3 priority levels. The “priority mapping” value is programmable. Figure 3-9 illustrates how the 802.
KSZ8795CLX The KSZ8795CLX supports common spanning tree (CST). To support spanning tree, the host port (Port 5) is the designated port for the processor. The other ports can be configured in one of the five spanning tree states via “transmit enable”, “receive enable” and “learning disable” register settings in: Port Control 2 Registers. Table 3-13 shows the port setting and software actions taken for each of the five spanning tree states.
KSZ8795CLX 3.6.3 RAPID SPANNING TREE SUPPORT There are three operational states of the discarding, learning, and forwarding assigned to each port for RSTP. Discarding ports do not participate in the active topology and do not learn MAC addresses. Ports in the learning states learn MAC addresses, but do not forward user traffic. Ports in the forwarding states fully participate in both data forwarding and MAC learning. RSTP uses only one type of BPDU called RSTP BPDUs.
KSZ8795CLX TABLE 3-15: TAIL TAG RULES Ingress to Port 5 (Host to KSZ8795CLX) Bits[3:0] Destination 0,0,0,0 Reserved 0,0,0,1 Port 1 (Direct forward to Port 1) 0,0,1,0 Port 2 (Direct forward to Port 2) 0,1,0,0 Port 3 (Direct forward to Port 3) 1,0,0,0 Port 4 (Direct forward to Port 4) 1,1,1,1 Port 1, 2, 3, and 4 (direct forward to Port 1, 2, 3, 4) Bits[7:4] — 0,0,0,0 Queue 0 is used at destination port 0,0,0,1 Queue 1 is used at destination port 0,0,1,0 Queue 2 is used at destination po
KSZ8795CLX For MLD snooping, tail tag mode also needs to be enabled, so that the processor knows which port the MLD packet was received on. This is achieved by setting Register 12 Bit[1]. 3.6.7 PORT MIRRORING SUPPORT The KSZ8795CLX supports “port mirror” as described in the following: 3.6.7.1 “Receive Only” Mirror on a Port All the packets received on the port will be mirrored on the sniffer port. For example, Port 1 is programmed to be “RX sniff,” and Port 5 is programmed to be the “sniffer port”.
KSZ8795CLX TABLE 3-16: FID+DA LOOK-UP IN VLAN MODE (CONTINUED) DA Found in Static MAC Table? Use FID Flag? FID Match? Yes 1 No Yes Send to the destination port defined in the Dynamic MAC Address Table Bits[58:56]. Yes 1 Yes Don’t Care Send to the destination port(s) defined in the Static MAC Address Table bits[52:48].
KSZ8795CLX TABLE 3-18: 10/100/1000 MBPS RATE SELECTION FOR THE RATE LIMIT (CONTINUED) Item Bps Bound of pps (Egress Only) 7d’114 7d’003 1664 pps 896 Kbps 1664 pps 896 Kbps 16640 pps 8960 Kbps 7d’115 7d’003 1792 pps 969 Kbps 1792 pps 969 Kbps 17920 pps 9690 Kbps 10 Mbps 100 Mbps 1000 Mbps The rate limit is independently on the “receive side” and on the “transmit side” on a per port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited.
KSZ8795CLX 3.6.9.3 Transmit Queue Ratio Programming In transmit queues 0-3 of the egress port, the default priority ratio is 8:4:2:1. The priority ratio can be programmed by the Port Control 10, 11, 12, and 13 registers. When the transmit rate exceeds the ratio limit in the transmit queue, the transmit rate will be limited by the transmit queue 0-3 ratio of the Port Control 10, 11, 12, and 13 registers. The highest priority queue will not be limited.
KSZ8795CLX 3.6.11.1 Authentication Register and Programming Model The port authentication control registers define the control of port-based authentication. The per-port authentication can be programmed in these registers. KSZ8795CLX provides three modes for implementing the IEEE 802.1x feature. Each mode can be selected by setting the appropriate bits in the port authentication registers.
KSZ8795CLX FIGURE 3-11: ACL FORMAT Matching Field • MD [1:0]: MODE There are three modes of operation defined in ACL. Mode 0 disables the current rule list, Mode 1 is qualification rules for Layer 2 MAC header filtering, Mode 2 is used for Layer 3 IP address filtering and Mode 3 performs Layer 4 TCP port number/protocol filtering. While mode 0 is selected, there will be no action taken. • ENB [1:0]: ENABLE Enables different rules in the current list.
KSZ8795CLX • • • • • • • • • • • If ENB = 01, the IP address and mask or IP protocol is enabled to be tested accordingly. If ENB = 10, source and destination addresses are compared. The drop/forward decision is based on the EQ bit setting. - When MD = 11 If ENB = 00, protocol comparison is enabled. If ENB = 01, TCP address comparison is selected. If ENB = 10, UDP address comparison is selected. If ENB = 11, the sequence number of the TCP is compared.
KSZ8795CLX - Group of rules to be qualified, there are 16 entries rule can be assigned to a rule set per port by the two ruleset registers. The rule table allows the rules to be cascaded. There are 16 entries in the RTB. Each entry can be a rule on its own, or can be cascaded with other entries to form a rule set. The test result of incoming packets against rule set will be the AND’ed result of all the test result of incoming packets against the rules included in this rule set.
KSZ8795CLX 4.0 DEVICE REGISTERS The KSZ8795CLX device has a rich set of registers available to manage the functionality of the device. Access to these registers is via the MIIM or SPI interfaces. Figure 4-1 provides a global picture of accessibility via the various interfaces and addressing ranges from the perspective of each interface.
KSZ8795CLX TABLE 4-1: MAPPING OF FUNCTIONAL AREAS WITHIN THE ADDRESS SPACE (CONTINUED) Register Locations Device Area 0x17 - 0x4F 4.1 PHY1 to PHY4 MIIM Registers Mapping to Those Port Registers’ Address Range Description The same PHY registers as specified in IEEE 802.3 specification.
KSZ8795CLX TABLE 4-2: DIRECT REGISTERS (CONTINUED) Address Contents 0xBF Reserved (Factory Testing Register): Transmit Queue Remap Base Register 0xC0-0xCE Port 2 Control Registers 0xCF Reserved (Factory Testing Register) 0xD0-0xDE Port 3 Control Registers 0xDF Reserved (Factory Testing Register) 0xE0-0xEE Port 4 Control Registers 0xEF Reserved (Factory Testing Register) 0xF0-0xFE Port 5 Control Registers 0xFF TABLE 4-3: Address Reserved (Factory Testing Register) GLOBAL REGISTERS Name
KSZ8795CLX TABLE 4-3: GLOBAL REGISTERS (CONTINUED) Address Name 4 Flush Static MAC Table Description Mode Default Flush the matched entries in static MAC table for RSTP 1 = Trigger the flush static MAC table operation. 0 = Normal operation. R/W (SC) 0 RO 1 Note: 3 The matched entry is defined as the entry in the Forwarding ports field contains a single port and MAC address with unicast. This port, in turn, has its learning capability being turned off (learning disable).
KSZ8795CLX TABLE 4-3: Address GLOBAL REGISTERS (CONTINUED) Name Description Mode Default R/W 1 Register 4 (0x04): Global Control 2 7 Unicast Port-VLAN Mismatch Discard This feature is used for port VLAN (described in Port Control 1 Register). 1 = All packets cannot cross VLAN boundary. 0 = Unicast packets (excluding unknown/multicast/ broadcast) can cross VLAN boundary. Note: When mirroring is enabled, the singledestination packets will be dropped if it’s mirrored to another port.
KSZ8795CLX TABLE 4-3: GLOBAL REGISTERS (CONTINUED) Address Name 0 Sniff Mode Select Description 1 = Enables Rx AND Tx sniff (both source port and destination port need to match). 0 = Enables Rx OR Tx sniff (Either source port or destination port need to match). Note: Mode Default R/W 0 Default is used to implement Rx only sniff. Register 6 (0x06): Global Control 4 7 Switch SW5-MII/RMII Back Pressure Enable 1 = Enable half-duplex back pressure on the switch MII/RMII interface.
KSZ8795CLX TABLE 4-3: Address GLOBAL REGISTERS (CONTINUED) Name Description Mode Default N/A Don’t Change RO 0x40 N/A Don’t Change RO 0x00 N/A Don’t Change RO 0 R/W 0 R/W 00 RO 0 Register 9 (0x09): Global Control 7 7-0 Factory Testing Register 10 (0x0A): Global Control 8 7-0 Factory Testing Register 11 (0x0B): Global Control 9 7 6 Reserved Port 5 SW5- RMII Refer- Select the data sampling edge of the SW5- RMII ence Clock Edge Select reference clock: 1 = Data sampling on the negative
KSZ8795CLX TABLE 4-3: GLOBAL REGISTERS (CONTINUED) Address Name 52 Reserved 1 Tail Tag Enable Description Mode Default N/A Don’t change. RO 0001 Tail Tag feature is applied for Port 5 only. R/W 0 1 = Switch will not filter 802.3x “flow control” packets. 0 = Switch will filter 802.3x “flow control” packets. R/W 0 N/A Don’t change. RO 00000000 N/A Don’t change.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 6 DiffServ Priority Classification Enable 5 4–3 Description Mode Default 1 = Enable DiffServ priority classification for ingress packets on port. 0 = Disable DiffServ function. R/W 0 802.1p Priority Classification Enable 1 = Enable 802.1p priority classification for ingress packets on port. 0 = Disable 802.1p priority classification for ingress packets on port.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name Description Mode Default 1 = Port is designated as Sniffer port and will transmit packets that are monitored. 0 = Port is a normal port.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 1 Receive Enable 0 Learning Disable Description Mode Default 1 = Enable packet reception on the port. 0 = Disable packet reception on the port. R/W 1 1 = Disable switch address learning capability. 0 = Enable switch address learning. R/W 0 Port’s default tag, containing: 7 5: User priority bits 4: CFI bit 3 0: VID[11:8] R/W 0 Default Port 1’s tag, containing: 7 0: VID[7:0] R/W 1 N/A Don’t change.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 6 Is_1Gbps Description 1 = 1Gbps is chosen for Port 5 in GMII/RGMII mode. 0 = 10/100 Mbps is chosen for Port 5 in GMII/ RGMII mode. Strap-in option: LED1_0 PU = 1Gbps in SW5-GMII/RGMII mode (Default) PD = 10/100 Mbps in SW5-GMII/RGMII mode Note: Mode Default R/W 1 RO 1 R/W 0 R/W 1 This pin has an internal pull-up. Use Bit[4] of the Register 6, Global Control 4 to set for 10 or 100 speed in 10/100 Mbps mode.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 2 GMII/MII Mode Select Description Mode Default R/W 1 R/W 11 N/A Don’t Change. RO 00 These bits indicate that the KSZ8795CLX has implemented both the optional MAC control sublayer and the PAUSE function as specified in IEEE Clause 31 and Annex 31B for full duplex operation independent of rate and medium. R/W 11 Port 5 GMAC5 SW5-GMII/MII Mode Select 1 = GMII/MII is in GMAC/MAC mode (Default). 0 = GMII/MII is in GPHY/PHY mode.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 3 Advertised 100BT FullDuplex Capability 2 Advertised 100BT HalfDuplex Capability 1 0 Description Mode Default 1 = Advertise 100BT full-duplex capability. 0 = Suppress 100BT full-duplex capability from transmission to link partner. R/W 1 1 = Advertise 100BT half-duplex capability. 0 = Suppress 100BT half-duplex capability from transmission to link partner.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name 2 Operation Speed 1 Operation Duplex 0 Reserved Register 26 (0x1A): Port 1 PHY Control 8 Register 42 (0x2A): Port 2 PHY Control 8 Register 58 (0x3A): Port 3 PHY Control 8 Register 74 (0x4A): Port 4 PHY Control 8 Register 90 (0x5A): Reserved 7 CDT 10M Short Note: Description Mode Default 1 = Link speed is 100 Mbps 0 = Link speed is 10 Mbps RO 0 1 = Link duplex is full 0 = Link duplex is half RO 0 N/A Don’t Change.
KSZ8795CLX TABLE 4-4: PORT REGISTERS (CONTINUED) Address Name Register 28 (0x1C): Port 1 Control 9 Register 44 (0x2C): Port 2 Control 9 Register 60 (0x3C): Port 3 Control 9 Register 76 (0x4C): Port 4 Control 9 Register 92 (0x5C): Reserved 7 Description Mode Default R/W 0 (Note 4-1) Disable Auto-Negotiation 1 = Disable Auto-Negotiation. Speed and duplex are decided by bits [6:5] of the same register. 0 = Auto-Negotiation is on.
KSZ8795CLX TABLE 4-4: Address PORT REGISTERS (CONTINUED) Name Register 30 (0x1E): Port 1 Status 2 Register 46 (0x2E): Port 2 Status 2 Register 62 (0x3E): Port 3 Status 2 Register 78 (0x4E): Port 4 Status 2 Register 94 (0x5E): Reserved Description Mode Default 1 = MDI. 0 = MDI-X. RO 0 1 = Auto-Negotiation done. 0 = Auto-Negotiation not done. RO 0 (Note 4-1) 7 MDIX Status 6 Auto-Negotiation Done 5 Link Good 1 = Link good. 0 = Link not good. RO 0 40 Reserved N/A Don’t Change.
KSZ8795CLX 4.3 Advanced Control Registers Registers 104 to 109 define the switching engine’s MAC address. This 48-bit address is used as the source address in MAC pause control frames.
KSZ8795CLX TABLE 4-6: ADVANCED CONTROL REGISTERS 110 - 111 (CONTINUED) Address Name 3-2 Table Select or Indirect Address [11:10] Description If bits [6:5] = 00, then 00 = Static MAC Address Table selected. 01 = VLAN table selected. 10 = Dynamic Address Table selected. 11 = MIB Counter selected. If bits [6:5] not equal 00, then These are indirect address [11:10] that is MSB of indirect address, Bits[11:8] of the indirect address may be served as port address, and Bits[7:0] as register address.
KSZ8795CLX TABLE 4-7: Address ADVANCED CONTROL REGISTERS 112 - 120 (CONTINUED) Name Description Mode Default R/W 00000000 R/W 00000000 R/W 00000000 R/W 00000000 Register 117 (0x75): Indirect Data Register 3 7-0 Indirect Data Bits[31:24] of indirect data [31:24] Register 118 (0x76): Indirect Data Register 2 7-0 Indirect Data Bits[23:16] of indirect data. [23:6] Register 119 (0x77): Indirect Data Register 1 7-0 Indirect Data Bits[15:8] of indirect data.
KSZ8795CLX TABLE 4-8: Address ADVANCED CONTROL REGISTERS 160, 124 - 127 (CONTINUED) Name Description Mode Default Register 125 (0x7D): Interrupt Mask Register 7-5 Reserved N/A Don’t Change. RO 000 4 PME Interrupt Mask 1 = Enable PME interrupt. 0 = Normal R/W 0 3 Port 4 Interrupt Mask 1 = Enable Port 4 interrupt. 0 = Normal R/W 0 2 Port 3 Interrupt Mask 1 = Enable Port 3 interrupt. 0 = Normal R/W 0 1 Port 2 Interrupt Mask 1 = Enable Port 2 interrupt.
KSZ8795CLX TABLE 4-9: ADVANCED CONTROL REGISTERS 128 - 129 (CONTINUED) Address Name 5-4 Tag_0x6 3-2 1-0 TABLE 4-10: Address Description Mode Default IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x6. R/W 0x3 Tag_0x5 IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x5. R/W 0x2 Tag_0x4 IEEE 802.1p mapping.
KSZ8795CLX TABLE 4-10: Address 5 4 -0 ADVANCED CONTROL REGISTERS 130 - 135 (CONTINUED) Name Description Mode Default Unknown 1 = Enable supporting unknown multicast packet Multicast forward Packet 0 = Disable Forward (not including IP multicast packet) R/W 0 Unknown Multicast Packet Forward Port Map R/W 00000 N/A Don’t Change.
KSZ8795CLX TABLE 4-10: ADVANCED CONTROL REGISTERS 130 - 135 (CONTINUED) Address Name 4-0 Unknown IP Multicast Packet Forward Port Map Description 00000 = Filter unknown IP multicast packet 00001 = Forward unknown IP multicast packet to Port 1 00011 = Forward unknown IP multicast packet to Port 1, Port 2 00111 = Forward unknown IP multicast packet to Port 1, Port 2, and Port 3 01111 = Forward unknown IP multicast packet to Port 1, Port 2, Port 3, and Port 4 11111 = Broadcast unknown IP multicast packet
KSZ8795CLX TABLE 4-11: ADVANCED CONTROL REGISTERS 144 - 159 (CONTINUED) Address Name 1-0 DSCP[1:0] Description Ipv4 and Ipv6 Mapping The value in this field is used as the frame’s priority when bits [7:2] of the frame’s IP OS/DiffServ/Traffic Class value is 0x00.
KSZ8795CLX TABLE 4-11: Address ADVANCED CONTROL REGISTERS 144 - 159 (CONTINUED) Name Description Mode Default Register 153 (0x99): TOS Priority Control Register 9 7-6 DSCP[79:78] Ipv4 and Ipv6 mapping _ for value 0x27 R/W 00 5-4 DSCP[77:76] Ipv4 and Ipv6 mapping _ for value 0x26 R/W 00 3-2 DSCP[75:74] Ipv4 and Ipv6 mapping _ for value 0x25 R/W 00 1-0 DSCP[73:72] Ipv4 and Ipv6 mapping _ for value 0x24 R/W 00 R/W 00 Register 154 (0x9A): TOS Priority Control Register 10 7-6 DSCP[87:86]
KSZ8795CLX TABLE 4-11: ADVANCED CONTROL REGISTERS 144 - 159 (CONTINUED) Address Name 1-0 DSCP [121:120] TABLE 4-12: Address Description Mode Default R/W 00 Mode Default N/A Don’t Change.
KSZ8795CLX TABLE 4-13: Address ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) Name Description Mode Default — RO 1 Port-based enable to pass all frames 1 = Enable 0 = Disable R/W 0 — RO 00 Register 176: Insert source Port 1 PVID for untagged frame at egress Port 5 Register 192: Insert source Port 2 PVID for untagged frame at egress Port 5 Register 208: Insert source Port 3 PVID for untagged frame at egress Port 5 Register 224: Insert source Port 4 PVID for untagged frame at egress Port 5 Reg
KSZ8795CLX TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED) Address Name 0 Insert Source Port PVID for Untagged Packet Destination to Lowest Egress Port Description Register 176: Insert source Port 1 PVID for untagged frame at egress Port 2 Register 192: Insert source Port 2 PVID for untagged frame at egress Port 1 Register 208: Insert source Port 3 PVID for untagged frame at egress Port 1 Register 224: Insert source Port 4 PVID for untagged frame at egress Port 1 Register 240:
KSZ8795CLX TABLE 4-13: Address ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED) Name Description Mode Default 0 = Strict priority, will transmit all the packets from this priority queue 2 before transmit lower priority queue. 1 = Bits[6:0] reflect the packet number allow to transmit from this priority queue 1 within a certain time. R/W 1 Port Trans- Packet number for Transmit Queue 2 for high/low mit Queue 2 priority packets in high/low priority packets in four Ratio[6:0] queues mode.
KSZ8795CLX TABLE 4-13: Address ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED) Name Description Mode Default 5 Ingress Limit 1 = Rate limit is counted based on number of Bit/Packets packet. Mode Select 0 = Rate limit is counted based on number of bit. R/W 0 4 Ingress Rate Limit Flow Control Enable 1 = Flow Control is asserted if the port’s receive rate is exceeded. 0 = Flow Control is not asserted if the port’s receive rate is exceeded.
KSZ8795CLX TABLE 4-13: Address 6-0 ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED) Name Description Port-Based Ingress Data Rate Limit For Priority 2 Frames Priority 2 Ingress traffic from this port is shaped according to Ingress Limit the Table 18 in “Rate Limiting Support” sub-section.
KSZ8795CLX TABLE 4-13: ADDITIONAL ADVANCED CONTROL REGISTERS (Note 4-1) (CONTINUED) Address Name 7 Reserved 6-0 Description — Port Queue 2 Egress Data Rate Limit For Priority 2 Frames Egress Limit Egress traffic from this port is shaped according to the Table 18 in “Rate Limiting Support” sub-section. In four queues mode, it is high/low priority.
KSZ8795CLX TABLE 4-15: INDIRECT REGISTER DESCRIPTIONS (CONTINUED) Control Indirect Address Direct Address 0x6E, Function Select Bits[7-5] = 000, Table_select Bits[3-2] = 11 0x000 – 0x08F, 0x100 – 0x109 Contents 0x000 – 0x01F Port 1 MIB Counters 0x020 – 0x03F Port 2 MIB Counters 0x040 – 0x05F Port 3 MIB Counters 0x060 – 0x07F Port 4 MIB Counters 0x080 – 0x09F Port 5 MIB Counters 0x100 – 0x113 Total Byte and Dropped MIB Counter Direct Address 0x6E, Function Select Bits[7-5] = 001, Bits[3-0] = Indirect
KSZ8795CLX TABLE 4-16: STATIC MAC ADDRESS TABLE (CONTINUED) Address Name 54 Override 53 Valid 52 - 48 Forwarding Ports 47 - 0 Description Mode Default 1 = Override spanning tree “transmit enable = 0” or “receive enable = 0* setting. This bit is used for spanning tree implementation. 0 = No override. RO 0 1 = This entry is valid, the look-up result will be used. 0 = This entry is not valid. RO 0 These 5 bits control the forward ports.
KSZ8795CLX Read Register 117 (31:24) Read Register 118 (23:16) Read Register 119 (15:8) Read Register 120 (7:0) 2. Static Address Table Write (write the 8th entry) Write Register 113 (62:56) Write Register 114 (55:48) Write Register 115 (47:40) Write Register 116 (39:32) Write Register 117 (31:24) Write Register 118 (23:16) Write Register 119 (15:8) Write Register 120 (7:0) Write to Register 110 with 0x00 (write static table selected) Write to Register 111 with 0x7 (trigger the write operation) 4.
KSZ8795CLX The VLAN table configuration is organized as 1024 VLAN sets, each VLAN set consists of four VLAN entries, to support up to 4096 VLAN entries. Each VLAN set has total 60 bits and three reversed bits are inserted between entries. Actually, 52 bits are used for the VLAN set which should be read or written at the same time specified by the indirect address.
KSZ8795CLX TABLE 4-18: VLAN ID AND INDIRECT REGISTERS (CONTINUED) Indirect Address High/Low Bit[9-0] for VLAN Sets Indirect Data Registers Bits for Each VLAN Entry 2 2 4.
KSZ8795CLX Read Register 115 (47:40) Read Register 116 (39:32) Read Register 117 (31:24) Read Register 118 (23:16) Read Register 119 (15:8) Read Register 120 (7:0) 2.
KSZ8795CLX TABLE 4-20: Address PME INDIRECT REGISTERS (CONTINUED) Name Description Mode Default Port PME Control Mask Register Reg. 110 (0x6E) Bits[7:5]=100 for PME, Reg. 110 Bits[3:0] = 0xn for port (n = 1, 2, 3, 4). Reg. 111 (0x6F) Bits[7:0]= Offset to access the Indirect Byte Register 0xA0. Offset: 0x04 (Bits[31:24]), 0x05 (Bits[23:16]), 0x06 (Bits[15:8]), 0x07 (Bits[7:0]). Location: (100 PME) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX 4.8 4.8.1 ACL Rule Table and ACL Indirect Registers ACL REGISTER AND PROGRAMMING MODEL The ACL registers are accessible by the microcontroller through a serial interface. The per-port register set is accessed through indirect addressing mechanism. The ACL entries are stored in the format shown in the following figure. Each ACL rule list table can input up to 16 entries per port, with a total of five ACL rule list tables that can be set for five ports.
KSZ8795CLX TABLE 4-21: Address ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES Name Description Mode Default Port_ACL_0 ACL Port Register 0 (0x00) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x00 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Address Name 3-2 ENB[1:0] Description ENABLE When MD=01: 00 = The 11 bits from PM, P, REP, MM in action field specify a count value for packets matching MAC Address and TYPE in matching field. The count unit is defined in FORWARD field Bit[4]; Bit[4] = 0, µs will be used. Bit[4] = 1, ms will apply. The FORWARDED field Bit[3] determines the algorithm used to generate interrupt when counter terminated.
KSZ8795CLX TABLE 4-21: Address ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Name Description Mode Default Port_ACL_3 ACL Port Register 3 (0x03) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x03 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-21: Address ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Name Description Mode Default Port_ACL_9 ACL Port Register 9 (0x09) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x09 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-21: Address ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Name Description Mode Default Port_ACL_7 ACL Port Register 7 (0x07) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x07 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Address Name Description 2-1 PC[1:0] 00 = The port comparison is disabled. 01 = Matching either one of MAX or MIN. 10 = Match if the port number is in the range of MAX and MIN. 11 = Match if the port number is out of the range 0 PRO[7] IP Protocol For the IP protocol to be matched Mode Default R/W 00 — 0 Port_ACL_5 ACL Port Register 5 (0x05) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg.
KSZ8795CLX TABLE 4-21: Address ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Name Description Mode Default Port_ACL_A ACL Port Register 10 (0x0A) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x0A to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-21: ACL INDIRECT REGISTERS FOR 14 BYTE ACL RULES (CONTINUED) Address Name 4-0 FORWARD [4:0] Description Port Map Each bit indicates forwarding decision of one port.
KSZ8795CLX TABLE 4-22: TEMPORAL STORAGE FOR 14 BYTES ACL RULES (CONTINUED) Address Name 5-0 BYTE_ENB [13:8] Description Byte Enable in ACL table; 14-Byte per entry Mode Default R/W 0 1 = Byte is selected for read/write 0 = Byte is not selected Bit[0] of BYTE_ENB[13:0] is for byte address 0x0D in ACL table entry, Bit[1] of BYTE_ENB[13:0] is for byte address 0x0C in ACL table entry, etc. Bit[13] of BYTE_ENB[13:0] is for byte address 0x00 in ACL table entry.
KSZ8795CLX TABLE 4-23: ACL READ/WRITE CONTROL (CONTINUED) Address 3-0 Name Description ACL_ENTRY ACL Entry Address _ADDRESS 0000 = Entry 0. 0001 = Entry 1. ….. 1111 = Entry 15. Mode Default R/W 0000 Port_ACL_ ACCESS_CONTROL2 ACL Port Register 17 (0x13) Reg. 110 (0x6E) Bits[7:5] = 010 for ACL, Reg. 110 Bits[3:0] = 0xn for Ports 1, 2, 3, 4, and 5. Reg. 111 (0x6F) Bits[7:0] = Offset 0x13 to access the Indirect Byte Register 0xA0. Location: (010 ACL) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX Write 0x00 to Register 111 (0x6F) // trigger the read/burst read operation(s) based on the Byte Enable Register setting by the Port 1 ACL access Register 0 (0x00). Read/Burst read the Indirect Byte Register 160 (0xA0) // to get data of ACL entry word 0, write 0x00 to 0x0D indirect address and read Register 160 (0xA0) after each byte address write to Register 111 (0x6F). Write Operation 1.
KSZ8795CLX TABLE 4-24: Address 7 6-0 EEE GLOBAL REGISTERS (CONTINUED) Name Description LPI 1 = LPI request will be stopped if input traffic is Terminated detected. By Input Traf- 0 = LPI request won’t be stopped by input traffic. fic Enable Reserved — Mode Default R/W 0 RO 0x10 EEE Global Register 1 Global Empty TXQ to LPI Wait Time Control Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register, Reg.
KSZ8795CLX TABLE 4-24: Address EEE GLOBAL REGISTERS (CONTINUED) Name Description Mode Default EEE Global Register 4 Global EEE Wakeup Error Threshold Control Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0x0 for the indirect global register, Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x38 (Bits[15:8]), 0x39 (Bits[7:0]) Location: (001 EEE) -> {0x0, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-25: Address 0 EEE PORT REGISTERS (CONTINUED) Name Description Link Partner 1 = Link Partner is Auto-Negotiation abled Auto-Negoti- 0 = Link Partner is not Auto-Negotiation abled ation Able Mode Default RO 0 EEE Port Register 1 Port Auto-Negotiation Next Page Transmit Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register , Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0.
KSZ8795CLX TABLE 4-25: Address EEE PORT REGISTERS (CONTINUED) Name Description Mode Default EEE Port Register 2 Port Auto-Negotiation Link Partner Next Page Receive Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register, Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x10 (Bits[15:8]), 0x11 (Bits[7:0]) Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-25: Address EEE PORT REGISTERS (CONTINUED) Name Description Mode Default EEE Port Register 3 Link Partner EEE Capability Status and Local Device EEE Capability Advisement Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register, Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x28 (Bits[15:8]), 0x29 (Bits[7:0]) Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-25: Address EEE PORT REGISTERS (CONTINUED) Name Description Mode Default EEE Port Register 5 Port EEE Control Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register, Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x2C (Bits[15:8]), 0x2D (bits[7:0]) Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-25: Address EEE PORT REGISTERS (CONTINUED) Name Description Mode Default EEE Port Register 6 Port EEE LPI Recovery Time Register Reg. 110 (0x6E) Bits[7:5] = 001 for EEE, Reg. 110 Bits[3:0] = 0xn, n = 1-4 for the Indirect Port Register, Reg. 111 (0x6F) Bits[7:0] = Offset to access the Indirect Byte Register 0xA0. Offset: 0x2E (Bits[15:8]), 0x2F (Bits[7:0]) Location: (001 EEE) -> {0xn, offset} -> 0xA0 holds the data.
KSZ8795CLX TABLE 4-26: Offset PORT MIB COUNTER INDIRECT MEMORY OFFSETS (CONTINUED) Counter Name Description 0x7 RxAlignmentError Rx packets within (64,1522) bytes w/a non-integral number of bytes and a bad CRC (upper limit depends on max packet size setting). 0x8 RxControl8808Pkts The number of MAC control frames received by a port with 88-08h in EtherType field. 0x9 RxPausePkts The number of PAUSE frames received by a port.
KSZ8795CLX TABLE 4-27: Address FORMAT OF PER-PORT MIB COUNTER Name Description Mode Default 1 = Counter overflow. 0 = No Counter overflow. RO 0 1 = Counter value is valid. 0 = Counter value is not valid.
KSZ8795CLX TABLE 4-30: FORMAT OF ALL DROPPED PACKET MIB COUNTER (IN TABLE 4-28) Address Name 38 Overflow 37 Count Valid 36 - 16 Reserved 15 - 0 Counter Values Description Mode Default 1 = Counter overflow. 0 = No Counter overflow. RO 0 1 = Counter value is valid. 0 = Counter value is not valid. RO 0 — RO All ‘0’ Counter value RO 0 Please note that all per-port MIB counters are Read-Clear.
KSZ8795CLX To read out all the counters, the best performance over the SPI bus is (160+3) × 8 × 20 = 26 µs, where there are 160 registers, 3 overhead, 8 clocks per access, at 50 MHz. In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the counters at least every 30 seconds. All port MIB counters are designed as “read clear.” 4.11 MIIM Registers All the registers defined in this section can be also accessed via the SPI interface.
KSZ8795CLX TABLE 4-31: MIIM REGISTERS (CONTINUED) Address Name 1 Disable Transmit 0 Description Mode Default 1 = Disable transmit. 0 = Normal operation. R/W 0 Disable LED 1 = Disable LED. 0 = Normal operation. R/W 0 0 = Not 100 BASET4 capable. RO 0 Register 1h: Basic Status 15 T4 Capable 14 100 Full Capable 1 = 100BASE-TX full-duplex capable. 0 = Not capable of 100BASE-TX full-duplex. RO 1 13 100 Half Capable 1 = 100BASE-TX half-duplex capable.
KSZ8795CLX TABLE 4-31: MIIM REGISTERS (CONTINUED) Address Name 4-0 Selector Field Description [00001] = IEEE 802.3 Mode Default RO 00001 Register 5h: Link Partner Ability 15 Reserved — RO 0 14 Reserved — RO 0 13 Reserved — RO 0 12 - 11 Reserved — RO 0 10 Pause 1 = Link partner flow control capable. 0 = Link partner not flow control capable. RO 0 9 Reserved — RO 0 8 Adv 100 Full 1 = Link partner 100BT full-duplex capable.
KSZ8795CLX TABLE 4-31: MIIM REGISTERS (CONTINUED) Address Name 3 Force_lnk 2 Mode Default 1 = Force link pass 0 = Normal operation R/W 0 Pwrsave 1 = Enable power save 0 = Disable power save R/W 0 1 Remote Loopback 1 = Perform Remote loopback, loop back path as follows: Port 1 (PHY ID address 0x1 Reg. 1fh, Bit[1] = ‘1’ Start: RXP1/RXM1 (Port 1) Loopback: PMD/PMA of Port 1’s PHY End: TXP1/TXM1 (Port 1) Setting PHY ID address 0x2, 3, 4, 5 Reg.
KSZ8795CLX 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VDD12A, VDD12D) ...................................................................................................................................... –0.5V to +1.8V (VDDAT, VDDIO) .......................................................................................................................................... –0.5V to +4.0V Input Voltage ......................................................................
KSZ8795CLX 6.0 ELECTRICAL CHARACTERISTICS VIN = 1.2V/3.3V (typical); TA = +25°C. Specification is for packaged product only. There is no additional transformer consumption due to use on chip termination technology with internal biasing for 10BASE-T and 100BASE-TX. The test condition is in Port 5 RGMII mode (default). Measurements were taken with operating ratings. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max.
KSZ8795CLX TABLE 6-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Parameters Output Low Voltage Output Tri-State Leakage Symbol VOL IOZ Min. Typ. Max. — — 0.4 — — 0.4 — — 0.3 — — 10 Units Note VDDIO = 3.3V V VDDIO = 2.5V VDDIO = 1.8V µA VIN = GND ~ VDDIO 100BASE-TX Transmit (measured differentially after 1:1 transformer) Peak Differential Output Voltage VO 0.95 — 1.
KSZ8795CLX 7.0 TIMING DIAGRAMS FIGURE 7-1: TABLE 7-1: GMII SIGNALS TIMING DIAGRAM GMII TIMING PARAMETERS Symbol Parameter — Clock Cycle — 8 — tIS Set-Up Time 1.2 — — tIH Hold Time 1.2 — — tOD Output Delay Respect to Clock Falling Edge — — 1 DS00002112B-page 116 Min. Typ. Max. Units ns 2016-2017 Microchip Technology Inc.
KSZ8795CLX FIGURE 7-2: RGMII V2.0 SPECIFICATION TXC (WITH INTERNAL DELAY ADDED) TXC (SOURCE OF DATA) TXD[8:5][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TXD[4] TXEN TXD[9 TXERR TXD[7:4][3:0] TX_CTL TsetupT TholdT TholdR TXC (AT RECEIVER) TsetupR RXC (WITH INTERNAL DELAY ADDED) RXC (SOURCE OF DATA) RXD[8:5][3:0] RXD[3:0] RXD[8:5] RXD[7:4] RXD[4] RXDV RXD[9 RXERR RXD[7:4][3:0] RX_CTL TsetupT TholdT RXC (AT RECEIVER) TholdR TsetupR TABLE 7-2: RGMII TIMING PARAMETERS Symbol Parameter Min. Typ.
KSZ8795CLX FIGURE 7-3: MAC MODE MII TIMING - DATA RECEIVED FROM MII RECEIVE TIMING FIGURE 7-4: MAC MODE MII TIMING - DATA TRANSMITTED FROM MII TRANSMIT TIMING TABLE 7-3: MAC MODE MII TIMING PARAMETERS Symbol Parameter tcyc3 10BASE-T/100BASE-TX Min. Typ. Max. Clock Cycle — 400/ 40 — 2 — — ts3 Set-Up Time th3 Hold Time 2 — — tov3 Output Valid 3 8 10 DS00002112B-page 118 Units ns 2016-2017 Microchip Technology Inc.
KSZ8795CLX FIGURE 7-5: PHY MODE MII TIMING - DATA RECEIVED FROM MII RECEIVE TIMING FIGURE 7-6: PHY MODE MII TIMING - DATA TRANSMITTED FROM MII TRANSMIT TIMING TABLE 7-4: PHY MODE MII TIMING PARAMETERS Symbol Parameter tcyc4 10BASET/100BASET Min. Typ. Max. Clock Cycle — 400/40 — ts4 Set-Up Time 10 — — th4 Hold Time 0 — — tov4 Output Valid 16 20 25 2016-2017 Microchip Technology Inc.
KSZ8795CLX FIGURE 7-7: RMII TIMING - DATA RECEIVED FROM RMII tCYC TRANSMIT TIMING REFCLK t1 t2 TX_EN TXD[1:0] FIGURE 7-8: RMII TIMING - DATA TRANSMITTED FROM RMII RECEIVE TIMING tCYC REFCLK CRSDV RXD[1:0] tOD TABLE 7-5: RMII TIMING PARAMETERS Symbol Parameter Min. Typ. tcyc Clock Cycle — 20 — t1 Set-Up Time 4 — — t2 Hold Time 2 — — tod Output Delay 3 — 10 DS00002112B-page 120 Max. Units ns 2016-2017 Microchip Technology Inc.
KSZ8795CLX FIGURE 7-9: SPI INPUT TIMING tSHSL SPIS_N tCHSL tCHSH tSLCH tSHCH SPIC tCHDL tDVCH tCHDX tCLCH LSB MSB SPID tDLDH tDHDL HIGH IMPEDANCE SPIQ TABLE 7-6: Symbol fC SPI INPUT TIMING PARAMETERS Parameter Min. Typ. Max.
KSZ8795CLX FIGURE 7-10: SPI OUTPUT TIMING SPIS_N tCH SPIC tCLQV tCL tSHQZ tCLQX SPIQ tQLQH tQHQL SPID TABLE 7-7: Symbol SPI OUTPUT TIMING PARAMETERS Parameter Min. Typ. Max.
KSZ8795CLX FIGURE 7-11: AUTO-NEGOTIATION TIMING FLP BURST FLP BURST TX+/TX– tFLPW tBTB CLOCK PULSE DATA PULSE tPW tPW CLOCK PULSE DATA PULSE TX+/TX– tCTD tCTC TABLE 7-8: Symbol AUTO-NEGOTIATION TIMING PARAMETERS Min. Typ. Max. FLP Burst to FLP Burst 8 16 24 FLP Burst Width — 2 — tPW Clock/Data Pulse Width — 100 — tCTD Clock Pulse to Data Pulse 55.5 64 69.
KSZ8795CLX FIGURE 7-12: MDC/MDIO TIMING tP MDC tMD1 MDIO (PHY INPUT) tMD2 VALID DATA VALID DATA tMD3 MDIO (PHY OUTPUT) TABLE 7-9: Symbol VALID DATA MDC/MDIO TYPICAL TIMING PARAMETERS Parameter fC Clock Frequency tP Min. Typ. Max. Units — 2.
KSZ8795CLX FIGURE 7-13: POWER-DOWN/POWER-UP AND RESET TIMING SUPPLY VOLTAGE tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN/OUTPUT PIN TABLE 7-10: Symbol RESET TIMING PARAMETERS Parameter tSR Stable Supply Voltages to Reset High Min. Typ. Max. Units 10 — — ms tCS Configuration Set-Up Time 5 — — tCH Configuration Hold Time 5 — — tRC Reset to Strap-In Pin Output 6 — — tVR 3.3V Rise Time 200 — — 2016-2017 Microchip Technology Inc.
KSZ8795CLX 8.0 RESET CIRCUIT The following discrete reset circuit, shown in Figure 8-1, is recommended when powering up the KSZ8795 device. For an application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc.), the reset circuit as shown in Figure 8-2 is recommended.
KSZ8795CLX 9.0 SELECTION OF ISOLATION TRANSFORMER One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements at line side. Request to separate the center taps of RX/ TX at chip side. The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5 dB. For the transmit line transformer, insertion loss of up to 1.
KSZ8795CLX 11.0 Note: PACKAGE OUTLINES For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging FIGURE 11-1: DS00002112B-page 128 80-LEAD 10 MM X 10 MM LQFP 2016-2017 Microchip Technology Inc.
KSZ8795CLX APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00002112B (01-05-17) DS00002112A (03-28-16) Section/Figure/Entry Correction All Sales listing and cover pages updated. Minor text changes throughout. Table 3-8, “Port 5 SW5-MII Connection,” on page 31 Updated right-most column header to be “MAC-toPHY Connection KSZ8795CLX SW5-MII MAC Mode.” Table 3-9, “Port 5 SW5-GMII Connection,” on page 31 Updated incorrect External GMAC column values.
KSZ8795CLX THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ8795CLX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
KSZ8795CLX NOTES: DS00002112B-page 132 2016-2017 Microchip Technology Inc.
KSZ8795CLX Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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