Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 9
KSZ8721BL/SL
Note 2-2 Speed: Low (100BASE-TX), High (10BASE-T)
Full-Duplex: Low (full-duplex), High (half-duplex)
Act: Toggle (transmit / receive activity)
Link: Low (link), High (no link)
Note 2-1 Strap-in is latched during power-up or reset.
Note 2-2 IPU = Input with internal pull-up.
IPD/O = Input with internal pull-down during reset; output pin otherwise.
IPU/O = Input with internal pull-up during reset; output pin otherwise.
See “Reference Circuit” section for pull-up/pull-down and float information.
Note 2-3 Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in
incorrect strapping values latched at reset. It is recommended that an external pull-down via 1 kΩ
resistor be used in these applications to augment the KSZ8721’s internal pull-down
TABLE 2-2: STRAPPING OPTIONS (Note 2-1)
Pin Number Pin Name Type (Note 2-2) Pin Function
6, 5, 4, 3
PHYAD[4:1]/
RXD[0:3]
IPD/O
PHY Address latched at power-up/reset. The default
PHY address is 00001.
25
PHYAD0/
INT#
IPU/O
Enables PCS_LPBK mode at power-up/reset. PD
(default) = Disable, PU = Enable.
9 (Note 2-3)
PCS_LPBK/
RXDV
IPD/O
Enables ISOLATE mode at power-up/reset. PD
(default) = Disable, PU = Enable.
11 (Note 2-3) ISO/RXER IPD/O
Enables RMII mode at power-up/reset. PD (default) =
Disable, PU = Enable.
21 (Note 2-3) RMII/COL IPD/O
Enable RMII back-to-back mode at power-up/reset. PD
(default) = Disable,
PU = Enable.
22 (Note 2-3)
RMII_BTB
CRS
IPD/O
Enable RMII back-to-back mode at power-up/reset. PD
(default) = Disable,
PU = Enable.
27
SPD100/
No FEF/
IPU/O
Latched into Register 0h bit 13 during power-up/reset.
PD = 10Mbps, PU (default) = 100Mbps. If SPD100 is
asserted during power-up/reset, this pin is also latched
as LED1 the Speed Support in register 4h. (If FXEN is
pulled up, the latched value 0 means no Far_End
_Fault.)
28
DUPLEX/
LED2
IPU/O
Latched into Register 0h bit 8 during power-up/reset.
PD = Half-duplex, PU (default) = Full-duplex. If Duplex
is pulled up during reset, this pin is also latched as the
Duplex support in register 4h.
29
NWAYEN/
LED3
IPU/O
Nway (auto-negotiation) Enable. Latched into Register
0h bit 12 during power-up/reset. PD = Disable Auto-
Negotiation, PU (default) = Enable Auto-Negotiation.
30 PD# IPU
Power-Down Enable. PU (default) = Normal operation,
PD = Power-Down mode.