Datasheet

KSZ8721BL/SL
DS00002813A-page 6  2018 Microchip Technology Inc.
TABLE 2-1: PIN DESCRIPTION
Pin
Number
Pin Name
Type
(Note 2-1)
Description
1 MDIO I/O
Management Independent Interface (MII) Data I/O. This pin
requires an external 4.7 kΩ pull-up resistor.
2 MDC I MII Clock Input. This pin is synchronous to the MDIO.
3
RXD3/PHYAD
IPD/O
MII Receive Data Output. RXD [3..0], these bits are synchronous
with RXCLK. When RXDV is asserted, RXD [3..0] presents valid
data to MAC through the MII. RXD [3..0] is invalid when RXDV is
de-asserted.
During reset, the pull-up/pull-down value is latched as PHYADDR
[1]. See Tab le 2- 2 for details.
4 RXD2/PHYAD2 IPD/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHY-
ADDR[2]. See Table 2-2 for details.
5 RXD1/PHYAD1 IPD/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHY-
ADDR[3]. See
Table 2-2
for details.
6 RXD0/PHYAD4 IPD/O
MII Receive Data Output.
During reset, the pull-up/pull-down value is latched as PHY-
ADDR[4]. See
Table 2-2
for details.
7 VDDIO P
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of
voltage regulator. See Section 3.23 “Circuit Design Reference
for Power Supply” for details.
8GNDGND
Ground.
9
RXDV/CRSDV/
PCS_LPBK
IPD/O
MII Receive Data Valid Output.
During reset, the pull-up/pull-down value is latched as
PCS_LPBK. See
Tab l e 2-2
for details.
10 RXC O
MII Receive Clock Output. Operating at 25 MHz = 100 Mbps,
2.5 MHz = 10 Mbps.
11 RXER/ISO IPD/O
MII Receive Error Output.
During reset, the pull-up/pull-down value is latched as ISOLATE
during reset. See
Table 2-2
for details.
12 GND GND Ground.
13 VDDC P
Digital core 2.5V only power supply. See Section 3.23 “Circuit
Design Reference for Power Supply” for details.
14 TXER IPD
MII Transmit Error Input.
15 TXC/REFCLK I/O
MII Transmit Clock Output.
Input for crystal or an external 50 MHz clock. When REFCLK pin
is used for REF clock interface, pull up XI to VDDPLL 2.5V via
10 kΩ resistor and leave XO pin unconnected.
16 TXEN IPD MII Transmit Enable Input.
17 TXD0
IPD MII Transmit Data Input.
18 TXD1 IPD MII Transmit Data Input.