Datasheet

KSZ8721BL/SL
DS00002813A-page 34  2018 Microchip Technology Inc.
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the device. The reset out from CPU/
FPGA provides warm reset after power up. It is also recommended to power up the V
DD
core voltage earlier than V
DDIO
voltage. At worst case, the both V
DD
core and V
DDIO
voltages should come up at the same time.
7.6.2 REFERENCE CIRCUIT FOR STRAPPING OPTION CONFIGURATION
Figure 7-9 shows the reference circuit for strapping option pins.
FIGURE 7-8: RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
FIGURE 7-9: REFERENCE CIRCUIT, STRAPPING OPTION PINS
VCC
R
Nȍ
D2
C
10μF
D1
CPU/FPGA
RST_OUT_n
KS8721BL/SL
RST
D1, D2: 1N4148
KS8721BL/SL
LED pin
2.5V
Reference circuits for unmanaged programming through LED ports.
KS8721BL/SL
LED pin
2.5V
Pull-Up
Pull-down
220:
220:
1k:
10k: