Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 33
KSZ8721BL/SL
7.6 Reset Timing
7.6.1 RESET CIRCUIT DIAGRAM
The following discrete reset circuit as shown in Figure 7-7 is recommended when powering up the KSZ8721BL/SL
device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), please
refer to the reset circuit as shown in Figure 7-8.
FIGURE 7-6: RESET TIMING
TABLE 7-6: RESET TIMING PARAMETERS
Parameter Symbol Min. Typ. Max. Units
Stable Supply Voltages to Reset High f
SR
50 — — µs
FIGURE 7-7: RECOMMENDED RESET CIRCUIT
tsr
Supply
Voltage
RST_N
Strap-In
Value