Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 29
KSZ8721BL/SL
7.2 100BASE-T MII Transmit Timing
Note 7-1 1BT = 10 ns at 100BASE-TX
FIGURE 7-2: 100BASE-T MII TRANSMIT TIMING
TABLE 7-2: 100BASE-T MII TRANSMIT TIMING PARAMETERS
Parameter Symbol Min. Typ. Max. Units
TXD [3:0] Set-Up to TXC High t
SU1
10 — — ns
TXEN Set-Up to TXC High t
SU2
10 — — ns
TXD [3:0] Hold After TXC High t
HD1
0—— ns
TXER Hold After TXC High t
HD2
0—— ns
TXEN Hold After TXC High t
HD3
0—— ns
TXEN High to CRS Asserted Latency t
CRS1
—4—BT (Note 7-1)
TXEN Low to CRS De-Asserted Latency t
CRS2
—4— BT
TXEN High to TXP/TXM Output (TX Latency) t
LAT
—9— BT
TXC
t
SU2
TXEN
t
HD2
TXD[3:0],
TXER
t
SU1
CRS
t
CRS2
t
C
RS1
TX+/TX-
t
LAT
t
HD1
Symbol
Out
Data
In