Datasheet

KSZ8721BL/SL
DS00002813A-page 24  2018 Microchip Technology Inc.
Note 4-1 RW = Read/Write
RO = Read Only
SC = Self Clear
LH = Latch High
LL = Latch Low
Some of the default values are set by strap-in. See Ta b le 2- 2 .
TABLE 4-13: REGISTER 1FH - 100BASE-TX PHY CONTROLLER
Bit Name Description Default Reference
1f.15:14 Reserved — RO 0
1f.13 Pairswap Disable
1 = Disable MDI/MDI-X
0 = Enable MDI/MDI-X
RW 0
1f.12 Energy Detect
1 = Presence of signal on RX+/RX– analog wire pair
0 = No signal detected on RX+/RX–
RO 0
1f.11 Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allow trans-
mitter to send pattern even if there is no link.
RW 0
1f.10 Power Saving
1 = Enable power-saving
0 = Disable
RW 1
1f.9 Interrupt Level
1 = Interrupt pin active high
0 = Active low
RW 0
1f.8 Enable Jabber
1 = Enable jabber counter
0 = Disable
RW 1
1f.7
Auto-Negotiation
Complete
1 = Auto-negotiation complete
0 = Not complete
RW 0
1f.6
Enable Pause
(Flow-Control Result)
1 = Flow control capable
0 = No flow control
RO 0
1f.5 PHY Isolate
1 = PHY in isolate mode
0 = Not isolated
RO 0
1f.4:2
Operation Mode
Indication
[000] = Still in auto-negotiation
[001] = 10BASE-T half-duplex
[010] = 100BASE-TX half-duplex
[011] = Reserved
[101] = 10BASE-T full-duplex
[110] = 100BASE-TX full-duplex
[111] = PHY/MII isolate
RO 0
1f.1 Enable SQE Test
1 = Enable SQE test
0 = Disable
RW 0
1f.0 Disable Data Scrambling
1 = Disable scrambler
0 = Enable
RW 0