Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 19
KSZ8721BL/SL
4.0 REGISTER MAP
TABLE 4-1: REGISTER DESCRIPTION
Register Number Description
0h Basic Control Register
1h Basic Status Register
2h PHY Identifier I
3h PHY Identifier II
4h Auto-Negotiation Advertisement Register
5h Auto-Negotiation Link Partner Ability Register
6h Auto-Negotiation Expansion Register
7h Auto-Negotiation Next Page Register
8h Link Partner Next Page Ability
15h RXER Counter Register
1 bh Interrupt Control/Status Register
1 fh 100BASE-TX PHY Control Register
TABLE 4-2: REGISTER 0H - BASIC CONTROL
Bit Name Description Default Reference
0.15 Reset 1 = Software reset. Bit is self-clearing RW/SC 0
0.14 Loop-Back
1 = Loop-back mode
0 = Normal operation
RW 0
0.13 Speed Select (LSB)
1 = 100 Mbps
0 = 10 Mbps
Ignored if Auto-Negotiation is enabled (0.12 = 1)
RW
Set by
SPD100
0.12 Auto-Negotiation Enable
1 = Enable auto-negotiation process
(override 0.13 and 0.8)
0 = Disable auto-negotiation process
RW
Set by
NWAYEN
0.11 Power Down
1 = Power-down mode
0 = Normal operation
RW 0
0.10 Isolate
1 = Electrical isolation of PHY from MII and TX+/
TX–
0 = Normal operation
RW Set by ISO
0.9 Restart Auto-Negotiation
1 = Restart auto-negotiation process
0 = Normal operation. Bit is self-clearing
RW/SC 0
0.8 Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
Set by
DUPLEX
0.7 Collision Test
1 = Enable COL test
0 = Disable COL test
RW 0
0.6:1 Reserved — RO 0
0.0
Disable
Transmitter
0 = Enable transmitter
1 = Disable transmitter
RW 0