Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 13
KSZ8721BL/SL
3.12 Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is,
in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when two noncontiguous zeroes in 10 bits are
detected, the carrier is detected.
Loss-of-carrier results in the deassertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV
remains continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is
negated prior to the first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, because the assertion of CRS_DV is
asynchronous relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes
place (see Section 3.13, Receive Data [1:0] (RXD[1:0])).
3.13 Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] trans-
fers two bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a
predetermined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle
when CRS_DV is deasserted. Values of RXD[1:0] other than “00” when CRS_DV is deasserted are reserved for out-of-
band signaling (to be defined). Values other than “00” on RXD[1:0] while CRS_DV is deasserted are ignored by the
MAC/repeater. Upon assertion of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes
place.
3.14 Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN
is asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are
presented to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transi-
tions synchronously with respect to REF_CLK.
3.15 Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is deasserted. Values of
TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signaling (to be defined). Values other
than “00” on TXD[1:0] while TX_EN is deasserted are ignored by the PHY.
3.16 Collision Detection
Because the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably
regenerates the COL signal of the MII by ANDing TX_EN and CRS_DV.
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers
as a self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL
signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was func-
tioning. Because the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.
3.17 RX_ER
The PHY provides RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-
11– Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a
coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-
layer) is detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously
with respect to REF_CLK. While CRS_DV is deasserted, RX_ER has no effect on the MAC.
TABLE 3-2: RMII AC CHARACTERISTICS
Symbol Parameter Min. Typ. Max. Units
— REF_CLK Frequency — 50 — MHz
— REF_CLK Duty Cycle 35 — 65 %