Datasheet

KSZ8721BL/SL
DS00002813A-page 12  2018 Microchip Technology Inc.
3.9.4 RECEIVE DATA VALID
The KSZ8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine
timing changes in the following way:
• For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last
nibble of the data packet.
• For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D” and
remains asserted until the end of the packet.
3.9.5 ERROR SIGNALS
Whenever the KSZ8721BL/SL receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on
the RXD pins. When the MAC asserts TXER, the KSZ8721BL/SL will drive “H” symbols (a Transmit Error defined in the
IEEE 802.3 4B/5B code group) out on the line to force signaling errors.
3.9.6 CARRIER SENSE (CRS)
For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-
of-stream delimiter, or /T/R symbol pair, causes deassertion of CRS. The PMA layer will also de-assert CRS if IDLE
symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is deasserted.
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and deassertion on reception of an end-
of-frame (EOF) marker.
3.9.7 COLLISION
Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KSZ8721BL/SL
asserts its collision signal, which is asynchronous to any clock.
3.10 RMII (Reduced MII) Data Interface
RMII interface specifies a low pin count, Reduced Media Independent Interface (RMII) intended for use between
Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
• It is capable of supporting 10 Mbps and 100 Mbps data rates.
• A single clock reference is sourced from the MAC to PHY (or from an external source).
• It provides independent 2-bit wide (di-bit) transmit and receive data paths.
• It uses TTL signal levels compatible with common digital CMOS ASIC processes.
3.11 Reference Clock (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0],
and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide
REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock
distribution device. Each PHY device must have an input corresponding to this clock but may use a single clock input
for multiple PHYs implemented on a single IC.
TABLE 3-1: RMII SIGNAL DEFINITION
Signal Name
Direction
(w/respect to the PHY)
Direction
(w/respect to the MAC)
Use
REF_CLK Input Input or Output
Synchronous clock reference
for receive, transmit and con-
trol interface
CRS_DV Output Input
Carrier Sense/Receive Data
Valid
RXD[1:0] Output Input Receive Data
TX_EN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data
RX_ER Output Input Receive Error