Datasheet

 2018 Microchip Technology Inc. DS00002813A-page 11
KSZ8721BL/SL
3.7 SQE and Jabber Function (10BASE-T Only)
In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a
test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL
goes high if TXEN is high for more than 20 ms (jabbering). If TXEN then goes low for more than 250 ms, the
10BASE-T transmitter is re-enabled and COL goes low.
3.8 Auto-Negotiation
The KSZ8721BL/SL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It
automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its
link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in
either full-duplex or half-duplex mode (please refer to ). Auto-negotiation is disabled in the FX mode.
During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the
conditions of power-on, link-loss, or restart. At the same time, the KSZ8721BL/SL monitors incoming data to determine
its mode of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or
100BASE-TX idle is detected. The operation mode is configured based on the following priority:
• Priority 1: 100BASE-TX, full-duplex
• Priority 2: 100BASE-TX, full-duplex
• Priority 3: 100BASE-TX, full-duplex
• Priority 4: 10BASE-T, half-duplex
When the KSZ8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring
acknowledge bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the
KSZ8721BL/SL detects the second code words, it then configures itself according to the above-mentioned priority. In
addition, the KSZ8721BL/SL also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the
KSZ8721BL/SL automatically configures to match the detected operating speed.
• A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).
• A specific protocol that runs across the above mentioned physical connection that allows one controller to commu-
nicate with multiple KSZ8721BL/SL devices. Each KSZ8721BL/SL is assigned an MII address between 0 and 31
by the PHYAD inputs.
• An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions are
specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.
The INTPRT pin functions as a management data interrupt in the MII. An active low or high in this pin indicates a status
change on the KSZ8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Reg-
ister bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.
3.9 MII Data Interface
The data interface consists of separate channels for transmitting data from a 10/100 802.3-compliant Media Access
Controller (MAC) to the KSZ8721BL/SL, and for receiving data from the line. Normal data transmission is implemented
in 4B nibble mode (4-bit wide nibbles).
3.9.1 TRANSMIT CLOCK (TXC)
The transmit clock is normally generated by the KSZ8721BL/SL from an external 25 MHz reference source at the X1
input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KSZ8721BL/SL
normally samples these signals on the rising edge of the TXC.
3.9.2 RECEIVE CLOCK (RXC)
For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-nego-
tiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive
clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle.
The KSZ8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize
the signals at the rising edge of the clock with 10 ns setup and hold times.
3.9.3 TRANSMIT ENABLE
The MAC must assert TXEN at the same time as the first nibble of the preamble, and deassert TXEN after the last bit
of the packet.