Datasheet

ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)Ethernet Transceiver LQFP 151mA MII / RMII

 2018 Microchip Technology Inc. DS00002813A-page 1

Features

• Single Chip 100BASE-TX/100BASE-FX/

10BASE-T Physical Layer Solution

• 2.5V CMOS Design; 2.5/3.3V Tolerance on I/O

• 3.3V Single Power Supply with Built-In Voltage

Regulator; Power Consumption <340 mW

(Including Output Driver Current)

• Fully Compliant to IEEE 802.3u Standard

• Supports MII and Reduced MII (RMII)

• Supports 10BASE-T, 100BASE-TX, and

100BASE-FX with Far-End Fault Detection

• Supports Power Down and Power Saving Modes

• Conﬁgurable Through MII Serial Management

Ports or via External Control Pin

• Supports Auto-Negotiation and Manual Selection

for 10/100 Mbps Speed and Full-Duplex/Half-

Duplex Modes

• On-Chip, Built-In, Analog Front-End Filtering for

Both 100BASE-TX and 10BASE-T

• LED Outputs for Link, Activity, Full-Duplex/Half-

Duplex, Collision, and Speed

• Supports Back-to-Back, FX to TX for Media

Converter Applications

• Supports MDI/MDI-X Auto-Crossover

• KSZ8721BL is a Drop-In Replacement for the

KSZ8721BT in the Same Footprint

• KSZ8721SL is a Drop-In Replacement for the

KSZ8721B in the Same Footprint

• Commercial Temperature Range: 0°C to +70°C

• Industrial Temperature Range: –40°C to +85°C

• Available in 48-pin SSOP and LQFP Packages

KSZ8721BL/SL

3.3V Single Power Supply 10/100 Base-TX/FX MII Physical Layer

Transceiver

Summary of content (44 pages)

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KSZ8721BL/SL 3.3V Single Power Supply 10/100 Base-TX/FX MII Physical Layer Transceiver Features • Single Chip 100BASE-TX/100BASE-FX/ 10BASE-T Physical Layer Solution • 2.5V CMOS Design; 2.5/3.3V Tolerance on I/O • 3.3V Single Power Supply with Built-In Voltage Regulator; Power Consumption <340 mW (Including Output Driver Current) • Fully Compliant to IEEE 802.
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KSZ8721BL/SL TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com.
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KS8721BL/SL Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ...................................................................
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KSZ8721BL/SL 1.0 INTRODUCTION 1.1 General Description Operating with a 2.5V core to meet low-voltage and low-power requirements, the KSZ8721BL and KSZ8721SL are 10BASE-T/100BASE-TX/FX Physical Layer Transceivers that use MII and RMII interfaces to transmit and receive data. They contain 10BASE-T Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical Coding Sub-layer (PCS) functions. The KSZ8721BL/SL also have on-chip 10BASE-T output ﬁltering.
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KSZ8721BL/SL 2.
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KSZ8721BL/SL TABLE 2-1: PIN DESCRIPTION Pin Number Pin Name Type (Note 2-1) 1 MDIO I/O 2 MDC I Description Management Independent Interface (MII) Data I/O. This pin requires an external 4.7 kΩ pull-up resistor. MII Clock Input. This pin is synchronous to the MDIO. 3 RXD3/PHYAD IPD/O MII Receive Data Output. RXD [3..0], these bits are synchronous with RXCLK. When RXDV is asserted, RXD [3..0] presents valid data to MAC through the MII. RXD [3..0] is invalid when RXDV is de-asserted.
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KSZ8721BL/SL TABLE 2-1: PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type (Note 2-1) 19 TXD2 IPD MII Transmit Data Input. 20 TXD3 IPD MII Transmit Data Input. 21 COL/RMII IPD/O MII Collision Detect Output. During reset, the pull-up/pull-down value is latched as RMII select. See Table 2-2 for details. Description 22 CRS/RMII_BTB IPD/O MII Carrier Sense Output. During reset, the pull-up/pull-down value is latched as RMII backto-back mode when RMII mode is selected.
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KSZ8721BL/SL TABLE 2-1: PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type (Note 2-1) 30 PD# IPU 31 VDDRX P Analog 2.5V power supply. See Section 3.23 “Circuit Design Reference for Power Supply” section for details. 32 RX– I Receive Input. Differential receive input pins for 100FX, 100BASE-TX, or 10BASE-T. 33 RX+ I Receive Input: Differential receive input pin for 100FX, 100BASETX, or 10BASE-T. 34 FXSD/ FXEN IPD/O Fiber Mode Enable/Signal Detect in Fiber Mode.
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KSZ8721BL/SL Note 2-2 Speed: Low (100BASE-TX), High (10BASE-T) Full-Duplex: Low (full-duplex), High (half-duplex) Act: Toggle (transmit / receive activity) Link: Low (link), High (no link) TABLE 2-2: STRAPPING OPTIONS (Note 2-1) Pin Number Pin Name Type (Note 2-2) Pin Function 6, 5, 4, 3 PHYAD[4:1]/ RXD[0:3] IPD/O PHY Address latched at power-up/reset. The default PHY address is 00001. 25 PHYAD0/ INT# IPU/O Enables PCS_LPBK mode at power-up/reset. PD (default) = Disable, PU = Enable.
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KSZ8721BL/SL 3.0 FUNCTIONAL DESCRIPTION 3.1 100BASE-TX transmit The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission. The circuitry starts with a parallel to serial conversion that converts the 25 MHz, 4-bit nibbles into a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal.
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KSZ8721BL/SL 3.7 SQE and Jabber Function (10BASE-T Only) In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL goes high if TXEN is high for more than 20 ms (jabbering). If TXEN then goes low for more than 250 ms, the 10BASE-T transmitter is re-enabled and COL goes low. 3.
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KSZ8721BL/SL 3.9.4 RECEIVE DATA VALID The KSZ8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine timing changes in the following way: • For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the ﬁrst nibble of the preamble to the last nibble of the data packet. • For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the ﬁrst nibble of the SFD “5D” and remains asserted until the end of the packet. 3.9.
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KSZ8721BL/SL 3.12 Carrier Sense/Receive Data Valid (CRS_DV) CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when two noncontiguous zeroes in 10 bits are detected, the carrier is detected. Loss-of-carrier results in the deassertion of CRS_DV synchronous to REF_CLK.
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KSZ8721BL/SL TABLE 3-2: RMII AC CHARACTERISTICS Symbol 3.18 Parameter Min. Typ. Max. Units tSU TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER 4 — — ns tH TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER Data Hold from REF_CLKRising Edge 2 — — ns Unused RMII Pins Input Pins TXD[2:3] and TXER are pull-down to GND Output Pins RXD[2:3] and RXC are no connect. Note that the RMII pin needs to be pulled up to enable RMII mode. 3.
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KSZ8721BL/SL FIGURE 3-2: CROSSOVER CABLE 10/100 Ethernet Media Dependent Interface 1 Receive Pair 10/100 Ethernet Media Dependent Interface Crossover Cable 1 Receive Pair 2 2 3 3 4 4 5 5 6 6 7 7 8 8 Transmit Pair Transmit Pair Modular Connector (RJ-45) HUB (Repeater or Switch) 3.
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KSZ8721BL/SL TABLE 3-3: 100BT FX MODE FXSD/FXEN Condition Less than 0.6V 100TX mode Less than 1.25V, but greater than 0.6V FX mode No signal detected FEF generated Greater than 1.25 FX mode Signal detected To ensure proper operation, the swing of ﬁber module SD should cover the threshold variation. A resistive voltage divider is recommended to adjust the SD voltage range.
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KSZ8721BL/SL 3.23 Circuit Design Reference for Power Supply Microchip’s integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM cost on both existing and future designs with the use of the new KSZ8721BL/SL single supply, single port 10/100 Ethernet PHY. FIGURE 3-4: CIRCUIT DESIGN The circuit design in Figure 7-1 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input power source and the 2.
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KSZ8721BL/SL Notes: DS00002813A-page 18  2018 Microchip Technology Inc.
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KSZ8721BL/SL 4.
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KSZ8721BL/SL TABLE 4-3: Bit 1.15 1.14 1.13 1.12 1.11 1.
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KSZ8721BL/SL TABLE 4-6: REGISTER 4H - AUTO-NEGOTIATION ADVERTISEMENT (CONTINUED) Bit Name Description Default Reference 4.10 Pause 1 = Pause function supported 0 = No pause function RW 0 4.9 100BASE-T4 1 = T4 capable 0 = No T4 capability RO 0 4.8 100BASE-TX Full-Duplex 1 = TX with full-duplex 0 = No TX full-duplex capability RW Set by SPD100 & DUPLEX 4.7 100BASE-TX 1 = TX capable 0 = No TX capability RW Set by SPD100 4.
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KSZ8721BL/SL TABLE 4-8: Bit REGISTER 6H - AUTO-NEGOTIATION EXPANSION Name Description Default Reference Reserved — RO 0 6.4 Parallel Detection Fault 1 = Fault detected by parallel detection 0 = No fault detected by parallel detection RO/LH 0 6.3 Link Partner Next Page Able 1 = Link partner has next page capability 0 = Link partner does not have next page capability RO 0 6.
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KSZ8721BL/SL TABLE 4-12: Bit REGISTER 1BH - INTERRUPT CONTROL/STATUS REGISTER Name Description Default Reference 1b.15 Jabber Interrupt Enable 1 = Enable jabber interrupt 0 = Disable jabber interrupt RW 0 1b.14 Receive Error Interrupt Enable 1 = Enable receive error interrupt 0 = Disable receive error interrupt RW 0 1b.13 Page Received Interrupt Enable 1 = Enable page received interrupt 0 = Disable page received interrupt RW 0 1b.
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KSZ8721BL/SL TABLE 4-13: Bit REGISTER 1FH - 100BASE-TX PHY CONTROLLER Name Description Default Reference Reserved — RO 0 1f.13 Pairswap Disable 1 = Disable MDI/MDI-X 0 = Enable MDI/MDI-X RW 0 1f.12 Energy Detect 1 = Presence of signal on RX+/RX– analog wire pair RO 0 = No signal detected on RX+/RX– 0 1f.11 Force Link 1 = Force link pass 0 = Normal link operation This bit bypasses the control logic and allow transmitter to send pattern even if there is no link. RW 0 1f.
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KSZ8721BL/SL 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Storage Temperature (TS)...................................................................................................................... –55°C to +150°C Supply Referenced to GND ...................................................................................................................... –0.5V to +4.0V All Pins ..........................................................................................................
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KSZ8721BL/SL 6.0 ELECTRICAL CHARACTERISTICS TABLE 6-1: ELECTRICAL CHARACTERISTICS (Note 6-1) VDD = 3.3V ±10% Parameters Symbol Min. Typ. Max.
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KSZ8721BL/SL TABLE 6-1: ELECTRICAL CHARACTERISTICS (Note 6-1) (CONTINUED) VDD = 3.3V ±10% Parameters Receive Clock, 10T Receive Clock Jitters Transmit Clock, 100TX Transmit Clock, 10T Transmit Clock Jitters Symbol RXC10 TXC100 TXC10 Min. Typ. Max. Units Conditions — 2.5 — — 3.0 — MHz — — 25 — MHz — — 2.5 — MHz — — 1.8 — ns(pp) — ns(pp) — Note 6-1 TA = 25°C. Specification for packaged product only.
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KSZ8721BL/SL 7.0 TIMING SPECIFICATIONS 7.1 10BASE-T MII Transmit Timing FIGURE 7-1: 10BASE-T MII TRANSMIT TIMING tHD2 TXC TXEN tSU2 TXD[3:0] CRS TXP/TXM tHD1 tSU1 tCRS1 tCRS2 tLA T Valid Data SQE Timing TXC TXEN COL TABLE 7-1: tSQE tSQEP 10BASE-T MII TRANSMIT TIMING PARAMETERS Parameter Symbol Min. Typ. Max.
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KSZ8721BL/SL 7.2 100BASE-T MII Transmit Timing FIGURE 7-2: 100BASE-T MII TRANSMIT TIMING TXC tHD2 tSU2 TXEN tHD1 tSU1 TXD[3:0], TXER Data In tCRS2 CRS tCRS1 tLAT TX+/TX- TABLE 7-2: Symbol Out 100BASE-T MII TRANSMIT TIMING PARAMETERS Parameter Symbol Min. Typ. Max.
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KSZ8721BL/SL 7.3 100BASE-T MII Receive Timing FIGURE 7-3: 100BASE-T MII RECEIVE TIMING RX+/RX- Start of Stream CRS RXDV RXD[3:0] RXER End of Stream tCRS1 tCRS2 tRLAT tSU tHD tWH RXC tWL tP TABLE 7-3: 100BASE-T MII RECEIVE TIMING PARAMETERS Parameter RXC Period Symbol Min. Typ. Max.
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KSZ8721BL/SL 7.4 Auto-Negotiation FIGURE 7-4: AUTO-NEGOTIATION/FAST LINK PULSE TIMING FLP Burst FLP Burst TX+/TX- tFLPW tBTB TX+/TX- Clock Pulse Data Pulse tPW tPW Clock Pulse Data Pulse tCTD tCTC TABLE 7-4: AUTO-NEGOTIATION/FAST LINK PULSE TIMING PARAMETERS Parameter FLP Burst to FLP Burst FLP Burst Width Symbol Min. Typ. Max.
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KSZ8721BL/SL 7.5 SMI Timing FIGURE 7-5: SERIAL MANAGEMENT INTERFACE TIMING tP MDC tMD1 MDIO (Into Chip) tMD2 Valid Data Valid Data tMD3 MDIO (Out of Chip) TABLE 7-5: Valid Data SERIAL MANAGEMENT INTERFACE TIMING PARAMETERS Parameter Symbol Min. Typ. Max.
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KSZ8721BL/SL 7.6 Reset Timing FIGURE 7-6: RESET TIMING Supply Voltage tsr RST_N Strap-In Value TABLE 7-6: RESET TIMING PARAMETERS Parameter Symbol Min. Typ. Max. Units fSR 50 — — µs Stable Supply Voltages to Reset High 7.6.1 RESET CIRCUIT DIAGRAM The following discrete reset circuit as shown in Figure 7-7 is recommended when powering up the KSZ8721BL/SL device. For the application where the reset circuit signal comes from another device (e.g.
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KSZ8721BL/SL FIGURE 7-8: RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET VCC R Nȍ D1 KS8721BL/SL CPU/FPGA RST RST_OUT_n D2 C 10μF D1, D2: 1N4148 At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the device. The reset out from CPU/ FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time. 7.6.
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KSZ8721BL/SL 7.7 Selection of Isolation Transformers One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated commonmode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics.
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KSZ8721BL/SL 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 48-Lead SSOP* MICREL XXXXXXXXX YYWWA4GXXXXXYYWWNNN 48-Lead LQFP* MICREL e3 MICREL KSZ8721SL 1736A4G000001736200 Example MICREL XXXXXXXXX KSZ8721BL YYWWA4O GXXXXXYYWWNNN 1641A4O Legend: XX...
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KSZ8721BL/SL FIGURE 8-1: Note: 48-LEAD LQFP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging.  2018 Microchip Technology Inc.
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KSZ8721BL/SL FIGURE 8-2: Note: 48-LEAD SSOP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002813A-page 38  2018 Microchip Technology Inc.
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KSZ8721BL/SL APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry DS00002813A (10-30-18) —  2018 Microchip Technology Inc. Correction Converted Micrel data sheet KSZ8721BL/SL to Microchip DS00002813A. Minor text changes throughout.
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KSZ8721BL/SL THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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KSZ8721BL/SL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Example: X -XX PART NO. X X Device Device: Package Supply Voltage Temperature Media Type a) KSZ8721-BL: 10/100 Base-TX/FX MII Physical Layer Transceiver, 48-Lead LQFP, Single 3.3V Supply, 0C to +70C,250/Tray b) KSZ8721-SL: 10/100 Base-TX/FX MII Physical Layer Transceiver, 48-Lead SSOP, Single 3.
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KSZ8721BL/SL NOTES: DS00002813A-page 42  2018 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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